From 7aec09ca69cc61e7e0cca42e635fa56ca61d72a8 Mon Sep 17 00:00:00 2001
From: Taylor R Campbell <riastradh@NetBSD.org>
Date: Wed, 2 Nov 2022 22:48:53 +0000
Subject: [PATCH] WIP: aarch64: emulate MRS xN,MIDR_EL1 at EL0 (userland)
---
sys/arch/aarch64/aarch64/trap.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/sys/arch/aarch64/aarch64/trap.c b/sys/arch/aarch64/aarch64/trap.c
index 6ac09810c447..7ad4dad19e1f 100644
--- a/sys/arch/aarch64/aarch64/trap.c
+++ b/sys/arch/aarch64/aarch64/trap.c
@@ -390,6 +390,7 @@ emul_aarch64_insn(struct trapframe *tf)
}
LE32TOH(insn);
+ printf("%s: insn=%"PRIx32"\n", __func__, insn);
if ((insn & 0xffffffe0) == 0xd53b0020) {
/* mrs x?,ctr_el0 */
unsigned int Xt = insn & 31;
@@ -400,7 +401,11 @@ emul_aarch64_insn(struct trapframe *tf)
tf->tf_reg[Xt] = ctr_el0;
}
curcpu()->ci_uct_trap.ev_count++;
-
+ } else if ((insn & 0xffffffe0) == 0xd5380000) {
+ /* mrs x?,midr_el1 */
+ unsigned int Xt = insn & 31;
+ if (Xt != 31)
+ tf->tf_reg[Xt] = reg_midr_el1_read();
} else {
return EMUL_ARM_UNKNOWN;
}
@@ -485,14 +490,19 @@ trap_el0_sync(struct trapframe *tf)
default:
case ESR_EC_UNKNOWN:
unknown:
+ printf("%s: esr=0x%"PRIx32"\n", __func__, esr);
#ifdef DDB
+ sigill_debug = 1;
if (sigill_debug) {
/* show illegal instruction */
+ uint32_t insn = 0;
+ ufetch_32((const uint32_t *)tf->tf_pc, &insn);
printf("TRAP: pid %d (%s), uid %d: %s:"
- " esr=0x%lx: pc=0x%lx: %s\n",
+ " esr=0x%lx: pc=0x%lx: 0x%"PRIx32" %s\n",
curlwp->l_proc->p_pid, curlwp->l_proc->p_comm,
l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1,
eclass_trapname(eclass), tf->tf_esr, tf->tf_pc,
+ insn,
strdisasm(tf->tf_pc, tf->tf_spsr));
}
#endif