From f3d53b83723a1a4de14c46f6f78438df9dd99a1a Mon Sep 17 00:00:00 2001 From: Taylor R Campbell Date: Thu, 31 Mar 2022 00:01:51 +0000 Subject: [PATCH 07/49] sparc/membar_ops: Upgrade membar_enter from R/RW to RW/RW. This will be deprecated soon but let's avoid leaving rakes to trip on with it arising from disagreement over the documentation (W/RW) and implementation and usage (R/RW). --- common/lib/libc/arch/sparc/atomic/membar_ops.S | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/common/lib/libc/arch/sparc/atomic/membar_ops.S b/common/lib/libc/arch/sparc/atomic/membar_ops.S index 9a56fec1a1dc..a1c780bf1089 100644 --- a/common/lib/libc/arch/sparc/atomic/membar_ops.S +++ b/common/lib/libc/arch/sparc/atomic/membar_ops.S @@ -39,10 +39,10 @@ /* * These assume Total Store Order (TSO), which may reorder - * store-before-load but nothing else. Hence, only membar_sync must - * issue anything -- specifically, an LDSTUB, which (along with SWAP) - * is the only instruction that implies a sequential consistency - * barrier. + * store-before-load but nothing else. Hence, only membar_sync (and + * its deprecated alias membar_enter) must issue anything -- + * specifically, an LDSTUB, which (along with SWAP) is the only + * instruction that implies a sequential consistency barrier. * * If we ran with Partial Store Order (PSO), we would also need to * issue STBAR for membar_exit (load/store-before-store) and @@ -66,8 +66,8 @@ END(_membar_sync) ATOMIC_OP_ALIAS(membar_producer,_membar_consumer) STRONG_ALIAS(_membar_producer,_membar_consumer) ATOMIC_OP_ALIAS(membar_consumer,_membar_consumer) -ATOMIC_OP_ALIAS(membar_enter,_membar_consumer) -STRONG_ALIAS(_membar_enter,_membar_consumer) +ATOMIC_OP_ALIAS(membar_enter,_membar_sync) +STRONG_ALIAS(_membar_enter,_membar_sync) ATOMIC_OP_ALIAS(membar_exit,_membar_consumer) STRONG_ALIAS(_membar_exit,_membar_consumer) ATOMIC_OP_ALIAS(membar_sync,_membar_sync)