From 4afe116e9805c0205c151853e7ce82ecdafee130 Mon Sep 17 00:00:00 2001
From: Taylor R Campbell <riastradh@NetBSD.org>
Date: Sun, 27 Feb 2022 19:43:11 +0000
Subject: [PATCH 14/49] mips/cavium: Insert appropriate membars around IPIs.

---
 sys/arch/mips/cavium/octeon_intr.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/sys/arch/mips/cavium/octeon_intr.c b/sys/arch/mips/cavium/octeon_intr.c
index 2fa9a89e0331..d259f48141ae 100644
--- a/sys/arch/mips/cavium/octeon_intr.c
+++ b/sys/arch/mips/cavium/octeon_intr.c
@@ -548,6 +548,7 @@ octeon_ipi_intr(void *arg)
 	ipi_mask &= mips3_ld(cpu->cpu_mbox_set);
 	if (ipi_mask == 0)
 		return 0;
+	membar_acquire();
 
 	mips3_sd(cpu->cpu_mbox_clr, ipi_mask);
 
@@ -566,8 +567,9 @@ octeon_ipi_intr(void *arg)
 #endif
 
 	/* if the request is clear, it was previously processed */
-	if ((ci->ci_request_ipis & ipi_mask) == 0)
+	if ((atomic_load_relaxed(&ci->ci_request_ipis) & ipi_mask) == 0)
 		return 0;
+	membar_acquire();
 
 	atomic_or_64(&ci->ci_active_ipis, ipi_mask);
 	atomic_and_64(&ci->ci_request_ipis, ~ipi_mask);
@@ -600,8 +602,10 @@ octeon_send_ipi(struct cpu_info *ci, int req)
 	const u_int ipi_shift = ipi_prio[req] == IPL_SCHED ? 16 : 0;
 	const uint32_t ipi_mask = __BIT(req + ipi_shift);
 
+	membar_release();
 	atomic_or_64(&ci->ci_request_ipis, ipi_mask);
 
+	membar_release();
 	mips3_sd(cpu->cpu_mbox_set, ipi_mask);
 
 	return 0;
-- 
2.33.0