From fe491f98b412de80fc5c8a560fae7a6bc13bfd5d Mon Sep 17 00:00:00 2001
From: Maya Rashish <coypu@sdf.org>
Date: Mon, 9 Jan 2017 00:21:53 +0200
Subject: [PATCH 1/8] Switch r10->r9, r11->r10. No functional change.

The intention is to use r11 later on, and it'd make sense
for the registers used to be sequential.
---
 crypto/aes/asm/aesni-sha1-x86_64.pl | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/crypto/aes/asm/aesni-sha1-x86_64.pl b/crypto/aes/asm/aesni-sha1-x86_64.pl
index a50795e..1a5a244 100644
--- a/crypto/aes/asm/aesni-sha1-x86_64.pl
+++ b/crypto/aes/asm/aesni-sha1-x86_64.pl
@@ -129,18 +129,18 @@ $code.=<<___;
 .align	32
 aesni_cbc_sha1_enc:
 	# caller should check for SSSE3 and AES-NI bits
-	mov	OPENSSL_ia32cap_P+0(%rip),%r10d
-	mov	OPENSSL_ia32cap_P+4(%rip),%r11
+	mov	OPENSSL_ia32cap_P+0(%rip),%r9d
+	mov	OPENSSL_ia32cap_P+4(%rip),%r10
 ___
 $code.=<<___ if ($shaext);
-	bt	\$61,%r11		# check SHA bit
+	bt	\$61,%r10		# check SHA bit
 	jc	aesni_cbc_sha1_enc_shaext
 ___
 $code.=<<___ if ($avx);
-	and	\$`1<<28`,%r11d		# mask AVX bit
-	and	\$`1<<30`,%r10d		# mask "Intel CPU" bit
-	or	%r11d,%r10d
-	cmp	\$`1<<28|1<<30`,%r10d
+	and	\$`1<<28`,%r10d		# mask AVX bit
+	and	\$`1<<30`,%r9d		# mask "Intel CPU" bit
+	or	%r10d,%r9d
+	cmp	\$`1<<28|1<<30`,%r9d
 	je	aesni_cbc_sha1_enc_avx
 ___
 $code.=<<___;
-- 
2.11.0