Index: sys/arch/arm/arm/cpufunc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm/cpufunc.c,v
retrieving revision 1.156
diff -u -p -r1.156 cpufunc.c
--- sys/arch/arm/arm/cpufunc.c	2 Jul 2015 08:33:31 -0000	1.156
+++ sys/arch/arm/arm/cpufunc.c	5 Oct 2015 16:02:00 -0000
@@ -3164,6 +3164,11 @@ armv7_setup(char *args)
 	if (vector_page == ARM_VECTORS_HIGH)
 		cpuctrl |= CPU_CONTROL_VECRELOC;
 #endif
+	uint32_t auxctrl = armreg_auxctl_read();
+	auxctrl |= __BIT(15);
+
+	/* Update auxctlr */
+	armreg_auxctl_write(auxctrl);
 
 	/* Clear out the cache */
 	cpu_idcache_wbinv_all();
Index: sys/arch/arm/cortex/a9_mpsubr.S
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/cortex/a9_mpsubr.S,v
retrieving revision 1.42
diff -u -p -r1.42 a9_mpsubr.S
--- sys/arch/arm/cortex/a9_mpsubr.S	9 Jun 2015 08:08:14 -0000	1.42
+++ sys/arch/arm/cortex/a9_mpsubr.S	5 Oct 2015 16:02:05 -0000
@@ -498,6 +498,10 @@ cortex_init:
 	bfi	r0, r2, #31, #1			// copy it to bit 31 in ACTRL
 #endif
 
+#if defined(CPU_CORTEXA15)
+	orr	r0, r0, #1<<15
+	orr	r0, r0, #1
+#endif
 #if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA9)
 	//
 	// Step 4a (continued on A5/A9), ACTLR.FW=1)