? a ? a1 ? a2 ? a3 ? a4 ? arch/evbarm/compile/JETSONTK1 ? arch/evbarm/stand/gzboot/ADI_BRH_flash_0x00140000/lib ? arch/evbarm/stand/gzboot/ADI_BRH_flash_0x00140000/vers.c Index: arch/arm/arm/cpufunc.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm/cpufunc.c,v retrieving revision 1.154 diff -u -p -r1.154 cpufunc.c --- arch/arm/arm/cpufunc.c 14 May 2015 05:39:32 -0000 1.154 +++ arch/arm/arm/cpufunc.c 30 May 2015 22:01:24 -0000 @@ -2132,7 +2132,7 @@ set_cpufuncs(void) #if defined(CPU_CORTEX) if (CPU_ID_CORTEX_P(cputype)) { cpufuncs = armv7_cpufuncs; - cpu_do_powersave = 1; /* Enable powersave */ + //cpu_do_powersave = 1; /* Enable powersave */ #if defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6) cpu_armv7_p = true; #endif Index: arch/arm/arm/cpufunc_asm.S =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm/cpufunc_asm.S,v retrieving revision 1.16 diff -u -p -r1.16 cpufunc_asm.S --- arch/arm/arm/cpufunc_asm.S 18 Aug 2013 06:28:18 -0000 1.16 +++ arch/arm/arm/cpufunc_asm.S 30 May 2015 22:01:24 -0000 @@ -129,6 +129,7 @@ ENTRY(cpufunc_control) it ne #endif mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */ + isb movs r0, r3 /* Return old value */ RET END(cpufunc_control) Index: arch/arm/arm/cpufunc_asm_armv7.S =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm/cpufunc_asm_armv7.S,v retrieving revision 1.24 diff -u -p -r1.24 cpufunc_asm_armv7.S --- arch/arm/arm/cpufunc_asm_armv7.S 30 May 2015 21:25:22 -0000 1.24 +++ arch/arm/arm/cpufunc_asm_armv7.S 30 May 2015 22:01:27 -0000 @@ -58,7 +58,7 @@ ENTRY(armv7_context_switch) #else mcr p15, 0, r0, c8, c7, 0 @ flush the I+D #endif - dsb + dsb @ Needed? Move into #else? isb bx lr END(armv7_context_switch) @@ -94,6 +94,13 @@ ENTRY(armv7_tlb_flushID_SE) #endif #endif /* !MULTIPROCESSOR */ dsb @ data synchronization barrier + + + mov r0, #0 + // A15 Errata 798181 + mcr p15, 0, r0, c8, c3, 1 + dsb + isb bx lr END(armv7_tlb_flushID_SE) @@ -124,6 +131,7 @@ END(armv7_tlb_flushID) ENTRY_NP(armv7_setttb) + dsb @ freebsd does this mrc p15, 0, ip, c0, c0, 5 @ get MPIDR cmp ip, #0 orrlt r0, r0, #0x5b @ MP, cachable (Normal WB) Index: arch/arm/arm32/arm32_tlb.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm32/arm32_tlb.c,v retrieving revision 1.9 diff -u -p -r1.9 arm32_tlb.c --- arch/arm/arm32/arm32_tlb.c 26 Mar 2015 08:45:05 -0000 1.9 +++ arch/arm/arm32/arm32_tlb.c 30 May 2015 22:01:27 -0000 @@ -131,6 +131,13 @@ tlb_invalidate_addr(vaddr_t va, tlb_asid //armreg_tlbiall_write(asid); } arm_dsb(); + + va = 0; + /* A15 errata 798181 */ + armreg_tlbimvais_write(va); + arm_dsb(); + + arm_isb(); } Index: arch/arm/arm32/pmap.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm32/pmap.c,v retrieving revision 1.322 diff -u -p -r1.322 pmap.c --- arch/arm/arm32/pmap.c 13 May 2015 15:33:47 -0000 1.322 +++ arch/arm/arm32/pmap.c 30 May 2015 22:01:38 -0000 @@ -3538,15 +3538,21 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { l2pte_reset(cleanlist[cnt].ptep); PTE_SYNC(cleanlist[cnt].ptep); + /* No obvious benefit to startup issue */ + pmap_tlb_flush_SE(pm, cleanlist[cnt].va & ~PAGE_MASK, flags & PAGE_MASK); + } l2pte_reset(ptep); PTE_SYNC(ptep); + + pmap_tlb_flush_SE(pm, sva, flags); + cleanlist_idx++; pm->pm_remove_all = true; } else { l2pte_reset(ptep); PTE_SYNC(ptep); - if (pm->pm_remove_all == false) { + if (true || pm->pm_remove_all == false) { pmap_tlb_flush_SE(pm, sva, flags); } } @@ -4868,6 +4874,9 @@ pmap_activate(struct lwp *l) */ UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); const uint32_t old_ttbcr = armreg_ttbcr_read(); + + + /* dsb any thing use TTBR0?? */ armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); arm_isb(); pmap_tlb_asid_acquire(npm, l); @@ -4947,6 +4956,8 @@ pmap_deactivate(struct lwp *l) * activated. */ const uint32_t old_ttbcr = armreg_ttbcr_read(); + + /* dsb to push out TTBR0 users ??? */ armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); arm_isb(); pmap_tlb_asid_deactivate(pm); @@ -7429,6 +7440,7 @@ pmap_pte_init_armv7(void) pte_l2_l_cache_mode |= L2_XS_S; pte_l2_s_cache_mode |= L2_XS_S; } + pmap_needs_pte_sync = 1; /* * Page tables are just all other memory. We can use write-back since Index: arch/evbarm/conf/JETSONTK1 =================================================================== RCS file: /cvsroot/src/sys/arch/evbarm/conf/JETSONTK1,v retrieving revision 1.27 diff -u -p -r1.27 JETSONTK1 --- arch/evbarm/conf/JETSONTK1 30 May 2015 15:36:27 -0000 1.27 +++ arch/evbarm/conf/JETSONTK1 30 May 2015 22:01:40 -0000 @@ -12,15 +12,15 @@ options CPU_CORTEXA15 options SOC_TEGRA124 options BOARD_JETSONTK1 options CPUFREQ_BOOT=2292 -#options MULTIPROCESSOR +options MULTIPROCESSOR #options MEMSIZE=2048 options DIAGNOSTIC # internal consistency checks options DEBUG -options LOCKDEBUG +#options LOCKDEBUG #options PMAP_DEBUG # Enable pmap_debug_level code #options IPKDB # remote kernel debugging -#options VERBOSE_INIT_ARM # verbose bootstraping messages +options VERBOSE_INIT_ARM # verbose bootstraping messages makeoptions DEBUG="-g" # compile full symbol table makeoptions COPY_SYMTAB=1 Index: arch/evbarm/conf/std.tegra =================================================================== RCS file: /cvsroot/src/sys/arch/evbarm/conf/std.tegra,v retrieving revision 1.5 diff -u -p -r1.5 std.tegra --- arch/evbarm/conf/std.tegra 4 May 2015 00:59:29 -0000 1.5 +++ arch/evbarm/conf/std.tegra 30 May 2015 22:01:40 -0000 @@ -20,10 +20,11 @@ options FPU_VFP options PCI_NETBSD_CONFIGURE options __HAVE_PCI_CONF_HOOK -makeoptions KERNEL_BASE_PHYS="0x81000000" -makeoptions KERNEL_BASE_VIRT="0x81000000" +makeoptions KERNEL_BASE_PHYS="0x80000000" +makeoptions KERNEL_BASE_VIRT="0x80000000" makeoptions BOARDTYPE="tegra" makeoptions BOARDMKFRAG="${THISARM}/conf/mk.tegra" +makeoptions LOADADDRESS="0x80000000" options ARM_INTR_IMPL="" options ARM_GENERIC_TODR