Index: sys/arch/arm/nvidia/tegra_ahcisata.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/nvidia/tegra_ahcisata.c,v
retrieving revision 1.9
diff -u -p -r1.9 tegra_ahcisata.c
--- sys/arch/arm/nvidia/tegra_ahcisata.c	22 Dec 2015 22:10:36 -0000	1.9
+++ sys/arch/arm/nvidia/tegra_ahcisata.c	24 Jun 2016 07:18:46 -0000
@@ -261,6 +261,10 @@ tegra_ahcisata_init(struct tegra_ahcisat
 	tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG,
 	    0, TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN);
 
+	/* Backdoor update the SPM capability bit*/
+	tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR,
+	    TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM, 0);
+
 	/* Enable access and bus mastering */
 	tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG1_REG,
 	    TEGRA_T_SATA0_CFG1_SERR |
Index: sys/arch/arm/nvidia/tegra_ahcisatareg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/nvidia/tegra_ahcisatareg.h,v
retrieving revision 1.2
diff -u -p -r1.2 tegra_ahcisatareg.h
--- sys/arch/arm/nvidia/tegra_ahcisatareg.h	15 Oct 2015 09:04:35 -0000	1.2
+++ sys/arch/arm/nvidia/tegra_ahcisatareg.h	24 Jun 2016 07:18:46 -0000
@@ -61,6 +61,9 @@
 #define TEGRA_SATA_AUX_RX_STAT_INT_REG		0x110c
 #define TEGRA_SATA_AUX_RX_STAT_INT_SATA_RX_STAT_INT_DISABLE	__BIT(2)
 
+#define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR		0x1300
+#define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM		__BIT(17)
+
 #define TEGRA_T_SATA0_BKDOOR_CC_REG		0x14a4
 #define TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE		__BITS(31,16)
 #define TEGRA_T_SATA0_BKDOOR_CC_PROG_IF			__BITS(15,8)