Index: sys/arch/evbarm/conf/std.rpi
===================================================================
RCS file: /cvsroot/src/sys/arch/evbarm/conf/std.rpi,v
retrieving revision 1.14
diff -u -p -r1.14 std.rpi
--- sys/arch/evbarm/conf/std.rpi	6 Apr 2014 12:43:18 -0000	1.14
+++ sys/arch/evbarm/conf/std.rpi	7 Apr 2014 14:40:52 -0000
@@ -9,7 +9,7 @@ include 	"arch/evbarm/conf/std.evbarm"
 include		"arch/evbarm/conf/files.rpi"
 
 options 	MODULAR
-options 	ARM11_COMPAT_MMU
+#options 	ARM11_COMPAT_MMU
 options 	__HAVE_CPU_COUNTER
 options 	__HAVE_FAST_SOFTINTS		# should be in types.h
 options 	__HAVE_CPU_UAREA_ALLOC_IDLELWP
Index: sys/arch/evbarm/rpi/rpi_start.S
===================================================================
RCS file: /cvsroot/src/sys/arch/evbarm/rpi/rpi_start.S,v
retrieving revision 1.10
diff -u -p -r1.10 rpi_start.S
--- sys/arch/evbarm/rpi/rpi_start.S	7 Apr 2014 14:40:17 -0000	1.10
+++ sys/arch/evbarm/rpi/rpi_start.S	7 Apr 2014 14:40:52 -0000
@@ -82,6 +82,7 @@
  */
 
 #include "opt_cputypes.h"
+#include "opt_cpuoptions.h"
 
 #include <machine/asm.h>
 #include <arm/armreg.h>
@@ -209,9 +210,23 @@ _C_LABEL(rpi_start):
 	mcr	p15, 0, r0, c7, c10, 4	/* Drain the write buffers. */
 
 	ldr	r0, Ltemp_l1_table	/* The page table address */
-	mcr	p15, 0, r0, c2, c0, 0	/* Set Translation Table Base */
 
-	mov	r0, #0
+	mcr	p15, 0, r0, c2, c0, 0	/* Set Translation Table Base 0 (TTB0) */
+
+#if defined(ARM_MMU_EXTENDED)
+	// When using split TTBRs, we need to set both since the physical
+	// addresses we were/are using might be in either.
+	mcr	p15, 0, r0, c2, c0, 1	/* TTBR1 write */
+#endif  
+
+#if defined(ARM_MMU_EXTENDED)
+	mov	r1, #TTBCR_S_N_1        /* make sure TTBCR_S_N is 1 */
+#else   
+	mov	r1, #0			/* make sure TTBCR is 0 */
+#endif
+	mcr	p15, 0, r1, c2, c0, 2	/* TTBCR write */
+  
+	mov     r0, #0
 	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate TLBs */
 
 	/* Set the Domain Access register.  Very important! */
@@ -267,6 +282,11 @@ Lstart:
 
 	/* bits to set in the Control Register */
 Lcontrol_set:
+#ifdef ARM11_COMPAT_MMU
+#define	CPU_CONTROL_EXTRA	0
+#else
+#define	CPU_CONTROL_EXTRA	CPU_CONTROL_XP_ENABLE
+#endif
 	.word CPU_CONTROL_MMU_ENABLE  | \
 	      CPU_CONTROL_AFLT_ENABLE | \
 	      CPU_CONTROL_DC_ENABLE   | \
@@ -278,7 +298,8 @@ Lcontrol_set:
 		(1 << 16) | 	/* SBO - Global enable for data tcm */ \
 		(1 << 18) |	/* SBO - Global enable for insn tcm */ \
 	      CPU_CONTROL_UNAL_ENABLE | \
-	      CPU_CONTROL_IC_ENABLE
+	      CPU_CONTROL_IC_ENABLE | \
+	      CPU_CONTROL_EXTRA
 
 
 	/* bits to clear in the Control Register */
@@ -306,20 +327,26 @@ Lctl_ID_dis:
 	.word	n_sec					    ; \
 	.word	attr					    ;
 
+#ifdef ARM11_COMPAT_MMU
+#define	L1_S_APv6_KRW		L1_S_AP_KRW
+#else
+#define	L1_S_APv6_KRW		L1_S_APv7_KRW
+#endif
+
 mmu_init_table:
 	/* Add 1MB of VA==PA at 0x00000000 so we can keep the kernel going */
 	MMU_INIT(0x0, 0x0,
 	    (_end - KERNEL_BASE + 2 * L1_S_SIZE - 1),
-	    L1_S_PROTO | L1_S_AP_KRW)
+	    L1_S_PROTO | L1_S_APv6_KRW)
 
 	MMU_INIT(KERNEL_BASE, 0x0,
 	    (_end - KERNEL_BASE + 2 * L1_S_SIZE - 1),
-	    L1_S_PROTO | L1_S_AP_KRW  | L1_S_B | L1_S_C)
+	    L1_S_PROTO | L1_S_APv6_KRW  | L1_S_B | L1_S_C)
 
 	/* Map the 16MB of peripherals */
 	MMU_INIT(RPI_KERNEL_IO_VBASE, RPI_KERNEL_IO_PBASE,
 	    (RPI_KERNEL_IO_VSIZE + L1_S_SIZE - 1),
-	    L1_S_PROTO | L1_S_AP_KRW)
+	    L1_S_PROTO | L1_S_APv6_KRW)
 
 	/* end of table */
 	MMU_INIT(0, 0, 0, 0)