? sys/cscope.out
? sys/arch/arm/include/arm32/pmap.h.armv6
Index: sys/arch/arm/arm/cpufunc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm/cpufunc.c,v
retrieving revision 1.147
diff -u -p -r1.147 cpufunc.c
--- sys/arch/arm/arm/cpufunc.c	18 Apr 2014 23:50:59 -0000	1.147
+++ sys/arch/arm/arm/cpufunc.c	27 Jul 2014 21:15:52 -0000
@@ -3153,10 +3153,11 @@ arm11x6_setup(char *args)
 		CPU_CONTROL_32BP_ENABLE |
 		CPU_CONTROL_32BD_ENABLE |
 		CPU_CONTROL_LABT_ENABLE |
-		CPU_CONTROL_SYST_ENABLE |
 		CPU_CONTROL_UNAL_ENABLE |
 #ifdef ARM_MMU_EXTENDED
 		CPU_CONTROL_XP_ENABLE   |
+#else
+		CPU_CONTROL_SYST_ENABLE |
 #endif
 		CPU_CONTROL_IC_ENABLE;
 
Index: sys/arch/arm/include/arm32/pmap.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/include/arm32/pmap.h,v
retrieving revision 1.133
diff -u -p -r1.133 pmap.h
--- sys/arch/arm/include/arm32/pmap.h	15 Jun 2014 03:27:46 -0000	1.133
+++ sys/arch/arm/include/arm32/pmap.h	27 Jul 2014 21:16:08 -0000
@@ -739,6 +739,7 @@ extern void (*pmap_zero_page_func)(paddr
 #define	L1_S_CACHE_MASK_generic	(L1_S_B|L1_S_C)
 #define	L1_S_CACHE_MASK_xscale	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X))
 #define	L1_S_CACHE_MASK_armv6	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX))
+#define	L1_S_CACHE_MASK_armv6n	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S)
 #define	L1_S_CACHE_MASK_armv7	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S)
 
 #define	L2_L_PROT_U_generic	(L2_AP(AP_U))
@@ -764,6 +765,7 @@ extern void (*pmap_zero_page_func)(paddr
 #define	L2_L_CACHE_MASK_generic	(L2_B|L2_C)
 #define	L2_L_CACHE_MASK_xscale	(L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X))
 #define	L2_L_CACHE_MASK_armv6	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX))
+#define	L2_L_CACHE_MASK_armv6n	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S)
 #define	L2_L_CACHE_MASK_armv7	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S)
 
 #define	L2_S_PROT_U_generic	(L2_AP(AP_U))
@@ -822,7 +824,11 @@ extern void (*pmap_zero_page_func)(paddr
 #else
 #define	L2_S_PROTO_armv6c	(L2_TYPE_S)	/* XP=0, subpage APs */
 #endif
+#ifdef ARM_MMU_EXTENDED
+#define	L2_S_PROTO_armv6n	(L2_TYPE_S|L2_XS_XN)
+#else
 #define	L2_S_PROTO_armv6n	(L2_TYPE_S)	/* with XP=1 */
+#endif
 #ifdef ARM_MMU_EXTENDED
 #define	L2_S_PROTO_armv7	(L2_TYPE_S|L2_XS_XN)
 #else
@@ -904,8 +910,8 @@ extern void (*pmap_zero_page_func)(paddr
 #define	L2_L_PROT_RO		L2_L_PROT_RO_armv6n
 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_armv6n
 
-#define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_armv6
-#define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_armv6
+#define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_armv6n
+#define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_armv6n
 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_armv6n
 
 /* These prototypes make writeable mappings, while the other MMU types
Index: sys/arch/arm/include/arm32/vmparam.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/include/arm32/vmparam.h,v
retrieving revision 1.34
diff -u -p -r1.34 vmparam.h
--- sys/arch/arm/include/arm32/vmparam.h	31 Mar 2014 01:48:37 -0000	1.34
+++ sys/arch/arm/include/arm32/vmparam.h	27 Jul 2014 21:16:08 -0000
@@ -44,6 +44,7 @@
  * Virtual Memory parameters common to all arm32 platforms.
  */
 
+#include <arm/cpuconf.h>
 #include <arm/arm32/pte.h>	/* pt_entry_t */
 
 #define	USRSTACK	VM_MAXUSER_ADDRESS
Index: sys/arch/evbarm/conf/std.rpi
===================================================================
RCS file: /cvsroot/src/sys/arch/evbarm/conf/std.rpi,v
retrieving revision 1.14
diff -u -p -r1.14 std.rpi
--- sys/arch/evbarm/conf/std.rpi	6 Apr 2014 12:43:18 -0000	1.14
+++ sys/arch/evbarm/conf/std.rpi	27 Jul 2014 21:16:10 -0000
@@ -9,7 +9,7 @@ include 	"arch/evbarm/conf/std.evbarm"
 include		"arch/evbarm/conf/files.rpi"
 
 options 	MODULAR
-options 	ARM11_COMPAT_MMU
+#options 	ARM11_COMPAT_MMU
 options 	__HAVE_CPU_COUNTER
 options 	__HAVE_FAST_SOFTINTS		# should be in types.h
 options 	__HAVE_CPU_UAREA_ALLOC_IDLELWP