Index: sys/arch/arm/arm/cpufunc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm/cpufunc.c,v
retrieving revision 1.157
diff -u -p -r1.157 cpufunc.c
--- sys/arch/arm/arm/cpufunc.c	15 Oct 2015 07:13:50 -0000	1.157
+++ sys/arch/arm/arm/cpufunc.c	23 Nov 2015 10:06:29 -0000
@@ -3147,6 +3147,7 @@ armv7_setup(char *args)
 
 	int cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_IC_ENABLE
 	    | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_BPRD_ENABLE
+	    | CPU_CONTROL_XP_ENABLE
 #ifdef __ARMEB__
 	    | CPU_CONTROL_EX_BEND
 #endif
@@ -3165,17 +3166,6 @@ armv7_setup(char *args)
 		cpuctrl |= CPU_CONTROL_VECRELOC;
 #endif
 
-#ifdef TEGRAK1_PMAP_WORKAROUND
-	uint32_t auxctrl = armreg_auxctl_read();
-
-	// u-boot sets this incorrectly on boot cpu
-	auxctrl &= ~CORTEXA15_ACTLR_BTB;
-	auxctrl |= CORTEXA15_ACTLR_IOBEU;
-
-	/* Update auxctlr */
-	armreg_auxctl_write(auxctrl);
-#endif
-
 	/* Clear out the cache */
 	cpu_idcache_wbinv_all();
 
Index: sys/arch/arm/arm32/arm32_kvminit.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm32/arm32_kvminit.c,v
retrieving revision 1.35
diff -u -p -r1.35 arm32_kvminit.c
--- sys/arch/arm/arm32/arm32_kvminit.c	1 Jun 2015 19:16:44 -0000	1.35
+++ sys/arch/arm/arm32/arm32_kvminit.c	23 Nov 2015 10:06:32 -0000
@@ -584,7 +584,7 @@ arm32_kernel_vm_init(vaddr_t kernel_vm_b
 		 * This page will just contain the system vectors and can be
 		 * shared by all processes.
 		 */
-		valloc_pages(bmi, &systempage, 1, VM_PROT_READ|VM_PROT_WRITE,
+		valloc_pages(bmi, &systempage, 1, VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE,
 		    PTE_CACHE, true);
 	}
 	systempage.pv_va = vectors;
@@ -684,7 +684,7 @@ arm32_kernel_vm_init(vaddr_t kernel_vm_b
 	text.pv_pa = bmi->bmi_kernelstart;
 	text.pv_va = KERN_PHYSTOV(bmi, bmi->bmi_kernelstart);
 	text.pv_size = textsize;
-	text.pv_prot = VM_PROT_READ|VM_PROT_WRITE; /* XXX VM_PROT_EXECUTE */
+	text.pv_prot = VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE;
 	text.pv_cache = PTE_CACHE;
 
 #ifdef VERBOSE_INIT_ARM
@@ -842,7 +842,7 @@ arm32_kernel_vm_init(vaddr_t kernel_vm_b
 	if (map_vectors_p) {
 		/* Map the vector page. */
 		pmap_map_entry(l1pt_va, systempage.pv_va, systempage.pv_pa,
-		    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+		    VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE, PTE_CACHE);
 	}
 
 	/* Map the Mini-Data cache clean area. */ 
Index: sys/arch/arm/arm32/pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm32/pmap.c,v
retrieving revision 1.330
diff -u -p -r1.330 pmap.c
--- sys/arch/arm/arm32/pmap.c	13 Nov 2015 08:04:21 -0000	1.330
+++ sys/arch/arm/arm32/pmap.c	23 Nov 2015 10:06:35 -0000
@@ -6598,8 +6598,13 @@ pmap_map_section(vaddr_t l1pt, vaddr_t v
 		break;
 	}
 
-	const pd_entry_t npde = L1_S_PROTO | pa |
+	pd_entry_t npde = L1_S_PROTO | pa |
 	    L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
+#ifdef ARM_MMU_EXTENDED
+	if (prot & VM_PROT_EXECUTE) {
+		npde &= ~L1_S_V6_XN;
+	}
+#endif
 	l1pte_setone(pdep + l1slot, npde);
 	PDE_SYNC(pdep + l1slot);
 }
@@ -6729,14 +6734,14 @@ pmap_map_chunk(vaddr_t l1pt, vaddr_t va,
 		/* See if we can use a supersection mapping. */
 		if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) {
 			/* Supersection are always domain 0 */
-			const pd_entry_t npde = L1_SS_PROTO | pa
-#ifdef ARM_MMU_EXTENDED_XXX
-			    | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN)
-#endif
+			pd_entry_t npde = L1_SS_PROTO | pa
 #ifdef ARM_MMU_EXTENDED
 			    | (va & 0x80000000 ? 0 : L1_S_V6_nG)
 #endif
 			    | L1_S_PROT(PTE_KERNEL, prot) | f1;
+#ifdef ARM_MMU_EXTENDED
+			npde &= ((prot & VM_PROT_EXECUTE) ? ~L1_S_V6_XN : ~0);
+#endif
 #ifdef VERBOSE_INIT_ARM
 			printf("sS");
 #endif
@@ -6750,15 +6755,15 @@ pmap_map_chunk(vaddr_t l1pt, vaddr_t va,
 #endif
 		/* See if we can use a section mapping. */
 		if (L1_S_MAPPABLE_P(va, pa, resid)) {
-			const pd_entry_t npde = L1_S_PROTO | pa
-#ifdef ARM_MMU_EXTENDED_XXX
-			    | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN)
-#endif
+			pd_entry_t npde = L1_S_PROTO | pa
 #ifdef ARM_MMU_EXTENDED
 			    | (va & 0x80000000 ? 0 : L1_S_V6_nG)
 #endif
 			    | L1_S_PROT(PTE_KERNEL, prot) | f1
 			    | L1_S_DOM(PMAP_DOMAIN_KERNEL);
+#ifdef ARM_MMU_EXTENDED
+			npde &= ((prot & VM_PROT_EXECUTE) ? ~L1_S_V6_XN : ~0);
+#endif
 #ifdef VERBOSE_INIT_ARM
 			printf("S");
 #endif
@@ -6787,14 +6792,14 @@ pmap_map_chunk(vaddr_t l1pt, vaddr_t va,
 
 		/* See if we can use a L2 large page mapping. */
 		if (L2_L_MAPPABLE_P(va, pa, resid)) {
-			const pt_entry_t npte = L2_L_PROTO | pa
-#ifdef ARM_MMU_EXTENDED_XXX
-			    | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN)
-#endif
+			pt_entry_t npte = L2_L_PROTO | pa
 #ifdef ARM_MMU_EXTENDED
 			    | (va & 0x80000000 ? 0 : L2_XS_nG)
 #endif
 			    | L2_L_PROT(PTE_KERNEL, prot) | f2l;
+#ifdef ARM_MMU_EXTENDED
+			npte &= ((prot & VM_PROT_EXECUTE) ? ~L2_XS_L_XN : ~0);
+#endif
 #ifdef VERBOSE_INIT_ARM
 			printf("L");
 #endif
@@ -6807,17 +6812,17 @@ pmap_map_chunk(vaddr_t l1pt, vaddr_t va,
 		}
 
 		/* Use a small page mapping. */
-#ifdef VERBOSE_INIT_ARM
-		printf("P");
-#endif
-		const pt_entry_t npte = L2_S_PROTO | pa
-#ifdef ARM_MMU_EXTENDED_XXX
-		    | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN)
-#endif
+		pt_entry_t npte = L2_S_PROTO | pa
 #ifdef ARM_MMU_EXTENDED
 		    | (va & 0x80000000 ? 0 : L2_XS_nG)
 #endif
 		    | L2_S_PROT(PTE_KERNEL, prot) | f2s;
+#ifdef ARM_MMU_EXTENDED
+		npte &= ((prot & VM_PROT_EXECUTE) ? ~L2_XS_XN : ~0);
+#endif
+#ifdef VERBOSE_INIT_ARM
+		printf("P");
+#endif
 		l2pte_set(ptep, npte, 0);
 		PTE_SYNC(ptep);
 		va += PAGE_SIZE;
Index: sys/arch/arm/cortex/a9_mpsubr.S
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/cortex/a9_mpsubr.S,v
retrieving revision 1.43
diff -u -p -r1.43 a9_mpsubr.S
--- sys/arch/arm/cortex/a9_mpsubr.S	15 Oct 2015 07:13:50 -0000	1.43
+++ sys/arch/arm/cortex/a9_mpsubr.S	23 Nov 2015 10:06:35 -0000
@@ -154,6 +154,7 @@ arm_boot_l1pt_init:
 	 CPU_CONTROL_AFLT_ENABLE_SET	|	\
 	 CPU_CONTROL_DC_ENABLE		|	\
 	 CPU_CONTROL_SWP_ENABLE		|	\
+	 CPU_CONTROL_XP_ENABLE		|	\
 	 CPU_CONTROL_BPRD_ENABLE	|	\
 	 CPU_CONTROL_IC_ENABLE		|	\
 	 CPU_CONTROL_EX_BEND_SET	|	\
@@ -498,10 +499,6 @@ cortex_init:
 	bfi	r0, r2, #31, #1			// copy it to bit 31 in ACTRL
 #endif
 
-#if defined(TEGRAK1_PMAP_WORKAROUND)
-	orr	r0, r0, #CORTEXA15_ACTLR_IOBEU
-#endif
-
 #if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA9)
 	//
 	// Step 4a (continued on A5/A9), ACTLR.FW=1)
Index: sys/arch/arm/include/arm32/pmap.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/include/arm32/pmap.h,v
retrieving revision 1.143
diff -u -p -r1.143 pmap.h
--- sys/arch/arm/include/arm32/pmap.h	11 Nov 2015 17:54:17 -0000	1.143
+++ sys/arch/arm/include/arm32/pmap.h	23 Nov 2015 10:06:36 -0000
@@ -807,17 +807,29 @@ extern void (*pmap_zero_page_func)(paddr
 #define	L1_S_PROTO_generic	(L1_TYPE_S | L1_S_IMP)
 #define	L1_S_PROTO_xscale	(L1_TYPE_S)
 #define	L1_S_PROTO_armv6	(L1_TYPE_S)
+#ifdef ARM_MMU_EXTENDED
+#define	L1_S_PROTO_armv7	(L1_TYPE_S | L1_S_V6_XN)
+#else
 #define	L1_S_PROTO_armv7	(L1_TYPE_S)
+#endif
 
 #define	L1_SS_PROTO_generic	0
 #define	L1_SS_PROTO_xscale	0
 #define	L1_SS_PROTO_armv6	(L1_TYPE_S | L1_S_V6_SS)
+#ifdef ARM_MMU_EXTENDED
+#define	L1_SS_PROTO_armv7	(L1_TYPE_S | L1_S_V6_SS | L1_S_V6_XN)
+#else
 #define	L1_SS_PROTO_armv7	(L1_TYPE_S | L1_S_V6_SS)
+#endif
 
 #define	L1_C_PROTO_generic	(L1_TYPE_C | L1_C_IMP2)
 #define	L1_C_PROTO_xscale	(L1_TYPE_C)
 #define	L1_C_PROTO_armv6	(L1_TYPE_C)
+#ifdef ARM_MMU_EXTENDED
+#define	L1_C_PROTO_armv7	(L1_TYPE_C | L1_S_V6_XN)
+#else
 #define	L1_C_PROTO_armv7	(L1_TYPE_C)
+#endif
 
 #define	L2_L_PROTO		(L2_TYPE_L)
 
Index: sys/arch/evbarm/conf/std.tegra
===================================================================
RCS file: /cvsroot/src/sys/arch/evbarm/conf/std.tegra,v
retrieving revision 1.9
diff -u -p -r1.9 std.tegra
--- sys/arch/evbarm/conf/std.tegra	18 Oct 2015 00:38:37 -0000	1.9
+++ sys/arch/evbarm/conf/std.tegra	23 Nov 2015 10:06:37 -0000
@@ -20,7 +20,6 @@ options 	FPU_VFP
 options 	PCI_NETBSD_CONFIGURE
 options 	__HAVE_PCI_CONF_HOOK
 options 	__BUS_SPACE_HAS_STREAM_METHODS
-options 	TEGRAK1_PMAP_WORKAROUND
 
 makeoptions	KERNEL_BASE_PHYS="0x81000000"
 makeoptions	KERNEL_BASE_VIRT="0x81000000"