Index: sys/arch/arm/arm32/pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm32/pmap.c,v
retrieving revision 1.303
diff -u -p -r1.303 pmap.c
--- sys/arch/arm/arm32/pmap.c	14 Oct 2014 12:31:14 -0000	1.303
+++ sys/arch/arm/arm32/pmap.c	19 Oct 2014 15:58:45 -0000
@@ -686,8 +686,8 @@ struct pv_entry {
 };
 
 /*
- * Macro to determine if a mapping might be resident in the
- * instruction cache and/or TLB
+ * Macros to determine if a mapping might be resident in the
+ * instruction/data cache and/or TLB
  */
 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED)
 /*
@@ -696,29 +696,16 @@ struct pv_entry {
  * flush.  If we used ASIDs then this would not be a problem.
  */
 #define	PV_BEEN_EXECD(f)  (((f) & PVF_EXEC) == PVF_EXEC)
+#define	PV_BEEN_REFD(f)   (1)
 #else
 #define	PV_BEEN_EXECD(f)  (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
+#define	PV_BEEN_REFD(f)   (((f) & PVF_REF) != 0)
 #endif
 #define	PV_IS_EXEC_P(f)   (((f) & PVF_EXEC) != 0)
 #define	PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0)
 #define	PV_IS_WRITE_P(f)  (((f) & PVF_WRITE) != 0)
 
 /*
- * Macro to determine if a mapping might be resident in the
- * data cache and/or TLB
- */
-#if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED)
-/*
- * Speculative loads by Cortex cores can cause TLB entries to be filled even if
- * there are no explicit accesses, so there may be always be TLB entries to
- * flush.  If we used ASIDs then this would not be a problem.
- */
-#define	PV_BEEN_REFD(f)   (1)
-#else
-#define	PV_BEEN_REFD(f)   (((f) & PVF_REF) != 0)
-#endif
-
-/*
  * Local prototypes
  */
 static bool		pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t);