diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index f7e58d0..29180db 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1154,6 +1154,20 @@ static int dap_rom_display(struct command_context *cmd_ctx,
 						break;
 					case 1:
 						subtype = "Processor";
+
+						uint32_t val;
+						retval = mem_ap_read_atomic_u32(dap,
+                                                	(component_base & 0xfffff000) | 0x000,
+                                                	&val);
+						if (retval == ERROR_OK) {
+							command_print(cmd_ctx, "\t\tDIDR is 0x%08" PRIx32", val);
+						}
+						retval = mem_ap_read_atomic_u32(dap,
+                                                	(component_base & 0xfffff000) | 0x0a0,
+                                                	&val);
+						if (retval == ERROR_OK) {
+							command_print(cmd_ctx, "\t\tPCSR is 0x%08" PRIx32", val);
+						}
 						break;
 					case 2:
 						subtype = "DSP";
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 4341aca..1d834fe 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -135,7 +135,9 @@ target_to_armv7a(struct target *target)
 /* See ARMv7a arch spec section C10.3 */
 #define CPUDBG_WFAR		0x018
 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
+#define CPUDBG_PCSR1		0x084
 #define CPUDBG_DSCR		0x088
+#define CPUDBG_PCSR0		0x0a0
 #define CPUDBG_DRCR		0x090
 #define CPUDBG_PRCR		0x310
 #define CPUDBG_PRSR		0x314