Index: sys/arch/mips/cavium/octeon_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/cavium/octeon_intr.c,v
retrieving revision 1.22
diff -u -p -r1.22 octeon_intr.c
--- sys/arch/mips/cavium/octeon_intr.c	5 Aug 2020 04:47:35 -0000	1.22
+++ sys/arch/mips/cavium/octeon_intr.c	17 Aug 2020 18:30:02 -0000
@@ -166,19 +166,26 @@ struct octeon_intrhand {
 static int octeon_send_ipi(struct cpu_info *, int);
 static int octeon_ipi_intr(void *);
 
-static struct octeon_intrhand ipi_intrhands[1] = {
+static struct octeon_intrhand ipi_intrhands[2] = {
 	[0] = {
 		.ih_func = octeon_ipi_intr,
 		.ih_arg = (void *)(uintptr_t)__BITS(15,0),
 		.ih_irq = CIU_INT_MBOX_15_0,
 		.ih_ipl = IPL_HIGH,
 	},
+	[1] = {
+		.ih_func = octeon_ipi_intr,
+		.ih_arg = (void *)(uintptr_t)__BITS(31,16),
+		.ih_irq = CIU_INT_MBOX_31_16,
+		.ih_ipl = IPL_SCHED,
+	},
 };
 #endif
 
 static struct octeon_intrhand *octciu_intrs[NIRQS] = {
 #ifdef MULTIPROCESSOR
 	[CIU_INT_MBOX_15_0] = &ipi_intrhands[0],
+	[CIU_INT_MBOX_31_16] = &ipi_intrhands[1],
 #endif
 };
 
@@ -256,6 +263,7 @@ octeon_intr_init(struct cpu_info *ci)
 #ifdef MULTIPROCESSOR
 	// Enable the IPIs
 	cpu->cpu_ip4_enable[0] |= __BIT(CIU_INT_MBOX_15_0);
+	cpu->cpu_ip3_enable[0] |= __BIT(CIU_INT_MBOX_31_16);
 #endif
 
 	if (ci->ci_dev) {
@@ -514,7 +522,8 @@ octeon_ipi_intr(void *arg)
 {
 	struct cpu_info * const ci = curcpu();
 	struct cpu_softc * const cpu = ci->ci_softc;
-	uint32_t ipi_mask = (uintptr_t) arg;
+	const uint32_t mbox_mask = (uintptr_t) arg;
+	uint32_t ipi_mask = mbox_mask;
 
 	KASSERTMSG(ci->ci_cpl == IPL_HIGH,
 	    "ipi_mask %#"PRIx32" cpl %d", ipi_mask, ci->ci_cpl);
@@ -525,7 +534,7 @@ octeon_ipi_intr(void *arg)
 
 	mips3_sd(cpu->cpu_mbox_clr, ipi_mask);
 
-	KASSERT(ipi_mask < __BIT(NIPIS));
+	KASSERT(__SHIFTOUT(ipi_mask, mbox_mask) < __BIT(NIPIS));
 
 #if NWDOG > 0
 	// Handle WDOG requests ourselves.
@@ -546,7 +555,7 @@ octeon_ipi_intr(void *arg)
 	atomic_or_64(&ci->ci_active_ipis, ipi_mask);
 	atomic_and_64(&ci->ci_request_ipis, ~ipi_mask);
 
-	ipi_process(ci, ipi_mask);
+	ipi_process(ci, __SHIFTOUT(ipi_mask, mbox_mask));
 
 	atomic_and_64(&ci->ci_active_ipis, ~ipi_mask);
 
@@ -571,7 +580,8 @@ octeon_send_ipi(struct cpu_info *ci, int
 		return -1;
 
 	struct cpu_softc * const cpu = ci->ci_softc;
-	const uint32_t ipi_mask = __BIT(req);
+	const u_int ipi_shift = req == IPI_SHOOTDOWN ? 16 : 0;
+	const uint32_t ipi_mask = __BIT(req + ipi_shift);
 
 	atomic_or_64(&ci->ci_request_ipis, ipi_mask);