? sys/cscope.out ? sys/arch/arm/arm/cpufunc_asm_armv7.S.testing Index: sys/arch/arm/allwinner/awin_board.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/allwinner/awin_board.c,v retrieving revision 1.24 diff -u -p -r1.24 awin_board.c --- sys/arch/arm/allwinner/awin_board.c 16 Oct 2014 00:04:35 -0000 1.24 +++ sys/arch/arm/allwinner/awin_board.c 20 Oct 2014 18:39:50 -0000 @@ -30,6 +30,7 @@ #include "opt_allwinner.h" #include "opt_arm_debug.h" +#include "opt_multiprocessor.h" #define _ARM32_BUS_DMA_PRIVATE @@ -220,6 +221,8 @@ awin_bootstrap(vaddr_t iobase, vaddr_t u #endif #if defined(MULTIPROCESSOR) || defined(VERBOSE_INIT_ARM) arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU); + arm_cpu_max = 1; + printf("%s: cpus clamped to 1\n", __func__); #endif #ifdef VERBOSE_INIT_ARM printf("%s: %d cpus present\n", __func__, arm_cpu_max); Index: sys/arch/arm/arm/arm_machdep.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm/arm_machdep.c,v retrieving revision 1.42 diff -u -p -r1.42 arm_machdep.c --- sys/arch/arm/arm/arm_machdep.c 14 Jun 2014 09:13:30 -0000 1.42 +++ sys/arch/arm/arm/arm_machdep.c 20 Oct 2014 18:39:50 -0000 @@ -75,6 +75,7 @@ #include "opt_cpuoptions.h" #include "opt_cputypes.h" #include "opt_arm_debug.h" +#include "opt_multiprocessor.h" #include Index: sys/arch/arm/arm/cpufunc.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm/cpufunc.c,v retrieving revision 1.150 diff -u -p -r1.150 cpufunc.c --- sys/arch/arm/arm/cpufunc.c 31 Jul 2014 07:14:42 -0000 1.150 +++ sys/arch/arm/arm/cpufunc.c 20 Oct 2014 18:39:51 -0000 @@ -3105,8 +3105,12 @@ void armv7_setup(char *args) { +#if 0 int cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_BPRD_ENABLE +#else + int cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_IC_ENABLE + | CPU_CONTROL_DC_ENABLE #ifdef __ARMEB__ | CPU_CONTROL_EX_BEND #endif @@ -3114,8 +3118,10 @@ armv7_setup(char *args) | CPU_CONTROL_AFLT_ENABLE; #endif | CPU_CONTROL_UNAL_ENABLE; +#endif int cpuctrlmask = cpuctrl | CPU_CONTROL_AFLT_ENABLE; + uint32_t auxctrl; cpuctrl = parse_cpu_options(args, armv7_options, cpuctrl); @@ -3131,6 +3137,15 @@ armv7_setup(char *args) /* Set the control register */ curcpu()->ci_ctrl = cpuctrl; cpu_control(cpuctrlmask, cpuctrl); + + /* Clear out the cache */ + cpu_idcache_wbinv_all(); + + auxctrl = (1 << 6) | (1<<0); + + /* Update auxctlr */ + armreg_auxctl_write(auxctrl); + } #endif /* CPU_ARMV7 */ Index: sys/arch/arm/arm/cpufunc_asm_armv7.S =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm/cpufunc_asm_armv7.S,v retrieving revision 1.18 diff -u -p -r1.18 cpufunc_asm_armv7.S --- sys/arch/arm/arm/cpufunc_asm_armv7.S 31 Jul 2014 06:26:06 -0000 1.18 +++ sys/arch/arm/arm/cpufunc_asm_armv7.S 20 Oct 2014 18:39:51 -0000 @@ -380,6 +380,7 @@ ENTRY_NP(armv7_dcache_inv_all) b 1b .Lnext_level_inv: + dsb mrc p15, 1, r0, c0, c0, 1 @ read CLIDR ubfx ip, r0, #24, #3 @ narrow to LoC add r3, r3, #2 @ go to next level @@ -440,6 +441,7 @@ ENTRY_NP(armv7_dcache_wbinv_all) b 1b .Lnext_level_wbinv: + dsb mrc p15, 1, r0, c0, c0, 1 @ read CLIDR ubfx ip, r0, #24, #3 @ narrow to LoC add r3, r3, #2 @ go to next level Index: sys/arch/arm/arm32/arm32_boot.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm32/arm32_boot.c,v retrieving revision 1.8 diff -u -p -r1.8 arm32_boot.c --- sys/arch/arm/arm32/arm32_boot.c 14 Sep 2014 20:35:45 -0000 1.8 +++ sys/arch/arm/arm32/arm32_boot.c 20 Oct 2014 18:39:51 -0000 @@ -127,6 +127,7 @@ __KERNEL_RCSID(1, "$NetBSD: arm32_boot.c #include "opt_ddb.h" #include "opt_kgdb.h" +#include "opt_multiprocessor.h" #include #include Index: sys/arch/arm/arm32/arm32_machdep.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm32/arm32_machdep.c,v retrieving revision 1.105 diff -u -p -r1.105 arm32_machdep.c --- sys/arch/arm/arm32/arm32_machdep.c 19 May 2014 22:47:53 -0000 1.105 +++ sys/arch/arm/arm32/arm32_machdep.c 20 Oct 2014 18:39:52 -0000 @@ -44,8 +44,9 @@ #include __KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.105 2014/05/19 22:47:53 rmind Exp $"); -#include "opt_modular.h" #include "opt_md.h" +#include "opt_modular.h" +#include "opt_multiprocessor.h" #include "opt_pmap_debug.h" #include Index: sys/arch/arm/arm32/arm32_tlb.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm32/arm32_tlb.c,v retrieving revision 1.4 diff -u -p -r1.4 arm32_tlb.c --- sys/arch/arm/arm32/arm32_tlb.c 14 Oct 2014 20:35:03 -0000 1.4 +++ sys/arch/arm/arm32/arm32_tlb.c 20 Oct 2014 18:39:52 -0000 @@ -29,6 +29,8 @@ #include __KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.4 2014/10/14 20:35:03 matt Exp $"); +#include "opt_multiprocessor.h" + #include #include @@ -50,6 +52,7 @@ tlb_set_asid(tlb_asid_t asid) arm_dsb(); if (asid == 0) { armreg_ttbcr_write(armreg_ttbcr_read() | TTBCR_S_PD0); + arm_isb(); } armreg_contextidr_write(asid); arm_isb(); @@ -118,15 +121,18 @@ tlb_invalidate_addr(vaddr_t va, tlb_asid #endif //armreg_tlbiall_write(asid); } + arm_dsb(); arm_isb(); } +#if 0 bool tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert_p) { tlb_invalidate_addr(va, asid); return true; } +#endif #if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA5) static u_int Index: sys/arch/arm/arm32/cpu.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm32/cpu.c,v retrieving revision 1.105 diff -u -p -r1.105 cpu.c --- sys/arch/arm/arm32/cpu.c 1 Sep 2014 13:43:31 -0000 1.105 +++ sys/arch/arm/arm32/cpu.c 20 Oct 2014 18:39:52 -0000 @@ -227,6 +227,16 @@ cpu_attach(device_t dv, cpuid_t id) } #endif +printf("pte_l1_s_cache_mask %08x\n", pte_l1_s_cache_mask); +printf("pte_l2_l_cache_mask %08x\n", pte_l2_l_cache_mask); +printf("pte_l2_s_cache_mask %08x\n", pte_l2_s_cache_mask); +printf("pte_l1_s_cache_mode %08x\n", pte_l1_s_cache_mode); +printf("pte_l2_l_cache_mode %08x\n", pte_l2_l_cache_mode); +printf("pte_l2_s_cache_mode %08x\n", pte_l2_s_cache_mode); +printf("pte_l1_s_cache_mode_pt %08x\n", pte_l1_s_cache_mode_pt); +printf("pte_l2_l_cache_mode_pt %08x\n", pte_l2_l_cache_mode_pt); +printf("pte_l2_s_cache_mode_pt %08x\n", pte_l2_s_cache_mode_pt); + vfp_attach(ci); /* XXX SMP */ } Index: sys/arch/arm/arm32/db_interface.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm32/db_interface.c,v retrieving revision 1.52 diff -u -p -r1.52 db_interface.c --- sys/arch/arm/arm32/db_interface.c 30 Mar 2014 08:00:34 -0000 1.52 +++ sys/arch/arm/arm32/db_interface.c 20 Oct 2014 18:39:52 -0000 @@ -39,6 +39,7 @@ __KERNEL_RCSID(0, "$NetBSD: db_interface #include "opt_ddb.h" #include "opt_kgdb.h" +#include "opt_multiprocessor.h" #include #include Index: sys/arch/arm/arm32/pmap.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/arm32/pmap.c,v retrieving revision 1.304 diff -u -p -r1.304 pmap.c --- sys/arch/arm/arm32/pmap.c 20 Oct 2014 07:13:27 -0000 1.304 +++ sys/arch/arm/arm32/pmap.c 20 Oct 2014 18:39:53 -0000 @@ -666,8 +666,8 @@ __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCK PR_NOWAIT, (pap))) /* - * We try to map the page tables write-through, if possible. However, not - * all CPUs have a write-through cache mode, so on those we have to sync + * We try to map the page tables write-through (wb?), if possible. However, not + * all CPUs have a write-through (wb?) cache mode, so on those we have to sync * the cache when we frob page tables. * * We try to evaluate this at compile time, if possible. However, it's @@ -1623,6 +1623,7 @@ pmap_free_l2_bucket(pmap_t pm, struct l2 #endif l1pte_setone(pdep, 0); PDE_SYNC(pdep); + /* XXXNH FLUSH */ #ifndef ARM_MMU_EXTENDED } #endif @@ -1650,6 +1651,7 @@ pmap_free_l2_bucket(pmap_t pm, struct l2 */ pm->pm_l2[L2_IDX(l1slot)] = NULL; pmap_free_l2_dtable(l2); + /* XXXNH Flush */ } /* @@ -1660,6 +1662,7 @@ static int pmap_l2ptp_ctor(void *arg, void *v, int flags) { #ifndef PMAP_INCLUDE_PTE_SYNC + well? vaddr_t va = (vaddr_t)v & ~PGOFSET; /* @@ -2497,11 +2500,14 @@ pmap_clearbit(struct vm_page_md *md, pad } if (npte != opte) { - l2pte_set(ptep, npte, opte); + l2pte_reset(ptep); PTE_SYNC(ptep); /* Flush the TLB entry if a current pmap. */ pmap_tlb_flush_SE(pm, va, oflags); + + l2pte_set(ptep, npte, 0); + PTE_SYNC(ptep); } pmap_release_pmap_lock(pm); @@ -2656,6 +2662,10 @@ pmap_syncicache_page(struct vm_page_md * for (size_t i = 0, j = 0; i < way_size; i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { + /* XXXNH I did this */ + l2pte_reset(ptep + j); + PTE_SYNC(ptep + j); + pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); /* * Set up a PTE with to flush these cache lines. @@ -2884,10 +2894,6 @@ pmap_page_remove(struct vm_page_md *md, pmap_release_page_lock(md); pmap_acquire_pmap_lock(pm); -#ifdef ARM_MMU_EXTENDED - pmap_tlb_invalidate_addr(pm, pv->pv_va); -#endif - l2b = pmap_get_l2_bucket(pm, pv->pv_va); KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); @@ -2910,6 +2916,12 @@ pmap_page_remove(struct vm_page_md *md, l2pte_reset(ptep); PTE_SYNC_CURRENT(pm, ptep); pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); + +#ifdef ARM_MMU_EXTENDED + /* XXXNH pmap_tlb_flush_SE()? */ + pmap_tlb_invalidate_addr(pm, pv->pv_va); +#endif + pmap_release_pmap_lock(pm); pool_put(&pmap_pv_pool, pv); @@ -3279,6 +3291,8 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_ #ifdef ARM_MMU_EXTENDED npte |= L2_XS_nG; /* user pages are not global */ #endif + } else { + KASSERT(!(npte & L2_XS_nG)); } /* @@ -3309,7 +3323,12 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_ */ if (npte != opte) { - l2pte_set(ptep, npte, opte); + /* XXXNH I did this */ + l2pte_reset(ptep); + PTE_SYNC(ptep); + pmap_tlb_flush_SE(pm, va, oflags); + + l2pte_set(ptep, npte, 0); PTE_SYNC(ptep); #ifndef ARM_MMU_EXTENDED bool is_cached = pmap_is_cached(pm); @@ -3330,6 +3349,7 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_ pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); if (*pdep != pde) { + /* XXXNH KASSERT *pde == 0 */ l1pte_setone(pdep, pde); PTE_SYNC(pdep); } @@ -3337,8 +3357,6 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_ } #endif /* !ARM_MMU_EXTENDED */ - pmap_tlb_flush_SE(pm, va, oflags); - #ifndef ARM_MMU_EXTENDED UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", is_cached, pm->pm_cstate.cs_all, 0, 0); @@ -3508,6 +3526,7 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd * Roll back the previous PTE list, * and zero out the current PTE. */ + /* XXXNH pmap_tlb_flush_SE()? */ for (cnt = 0; cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { l2pte_reset(cleanlist[cnt].ptep); @@ -3532,6 +3551,9 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { total += cleanlist_idx; for (cnt = 0; cnt < cleanlist_idx; cnt++) { + /* XXXNH I did this */ + l2pte_reset(cleanlist[cnt].ptep); + PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); #ifdef ARM_MMU_EXTENDED vaddr_t clva = cleanlist[cnt].va; pmap_tlb_flush_SE(pm, clva, PVF_REF); @@ -3548,8 +3570,6 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd PVF_REF | flags); } #endif /* ARM_MMU_EXTENDED */ - l2pte_reset(cleanlist[cnt].ptep); - PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); } /* @@ -3683,6 +3703,8 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, v } #endif if (l2pte_valid_p(opte)) { + l2pte_reset(ptep); + PTE_SYNC(ptep); #ifdef PMAP_CACHE_VIVT cpu_dcache_wbinv_range(va, PAGE_SIZE); #endif @@ -3700,7 +3722,7 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, v if (prot & VM_PROT_EXECUTE) npte &= ~L2_XS_XN; #endif - l2pte_set(ptep, npte, opte); + l2pte_set(ptep, npte, 0); PTE_SYNC(ptep); if (pg) { @@ -3871,13 +3893,13 @@ pmap_extract(pmap_t pm, vaddr_t va, padd * These should only happen for pmap_kernel() */ KDASSERT(pm == pmap_kernel()); - pmap_release_pmap_lock(pm); #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 if (l1pte_supersection_p(pde)) { pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); } else #endif pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); + pmap_release_pmap_lock(pm); } else { /* * Note that we can't rely on the validity of the L1 @@ -3940,9 +3962,11 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad pmap_acquire_pmap_lock(pm); +#ifndef ARM_MMU_EXTENDED const bool flush = eva - sva >= PAGE_SIZE * 4; - u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); u_int flags = 0; +#endif + u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); while (sva < eva) { next_bucket = L2_NEXT_BUCKET_VA(sva); @@ -3961,7 +3985,9 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad const pt_entry_t opte = *ptep; if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { struct vm_page *pg; +#ifndef ARM_MMU_EXTENDED u_int f; +#endif #ifdef PMAP_CACHE_VIVT /* @@ -3975,7 +4001,12 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); pt_entry_t npte = l2pte_set_readonly(opte); - l2pte_set(ptep, npte, opte); + l2pte_reset(ptep); + PTE_SYNC(ptep); +#ifdef ARM_MMU_EXTENDED + pmap_tlb_flush_SE(pm, sva, PVF_REF); +#endif + l2pte_set(ptep, npte, 0); PTE_SYNC(ptep); if (pg != NULL) { @@ -3983,10 +4014,14 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad paddr_t pa = VM_PAGE_TO_PHYS(pg); pmap_acquire_page_lock(md); - f = pmap_modify_pv(md, pa, pm, sva, - clr_mask, 0); +#ifndef ARM_MMU_EXTENDED + f = +#endif + pmap_modify_pv(md, pa, pm, sva, + clr_mask, 0); pmap_vac_me_harder(md, pa, pm, sva); pmap_release_page_lock(md); +#ifndef ARM_MMU_EXTENDED } else { f = PVF_REF | PVF_EXEC; } @@ -3995,6 +4030,7 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad flags |= f; } else { pmap_tlb_flush_SE(pm, sva, f); +#endif } } @@ -4003,6 +4039,7 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad } } +#ifndef ARM_MMU_EXTENDED if (flush) { if (PV_BEEN_EXECD(flags)) { pmap_tlb_flushID(pm); @@ -4010,6 +4047,7 @@ pmap_protect(pmap_t pm, vaddr_t sva, vad pmap_tlb_flushD(pm); } } +#endif pmap_release_pmap_lock(pm); } @@ -4208,12 +4246,15 @@ pmap_prefetchabt_fixup(void *v) KASSERT(pv != NULL); if (PV_IS_EXEC_P(pv->pv_flags)) { + l2pte_reset(ptep); + PTE_SYNC(ptep); + pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); if (!PV_IS_EXEC_P(md->pvh_attrs)) { pmap_syncicache_page(md, pa); } rv = ABORT_FIXUP_RETURN; - l2pte_set(ptep, opte & ~L2_XS_XN, opte); - pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); + l2pte_set(ptep, opte & ~L2_XS_XN, 0); + PTE_SYNC(ptep); } pmap_release_page_lock(md); @@ -4359,7 +4400,11 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va, | (pm != pmap_kernel() ? L2_XS_nG : 0) #endif | 0; - l2pte_set(ptep, npte, opte); + l2pte_reset(ptep); + PTE_SYNC(ptep); + pmap_tlb_flush_SE(pm, va, + (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); + l2pte_set(ptep, npte, 0); PTE_SYNC(ptep); PMAPCOUNT(fixup_mod); rv = 1; @@ -4397,6 +4442,8 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va, #ifdef ARM_MMU_EXTENDED if (pm != pmap_kernel()) { npte |= L2_XS_nG; + } else { + KASSERT(!(npte & L2_XS_nG)); } /* * If we got called from prefetch abort, then ftype will have @@ -4426,7 +4473,11 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va, } #endif /* ARM_MMU_EXTENDED */ pmap_release_page_lock(md); - l2pte_set(ptep, npte, opte); + l2pte_reset(ptep); + PTE_SYNC(ptep); + pmap_tlb_flush_SE(pm, va, + (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); + l2pte_set(ptep, npte, 0); PTE_SYNC(ptep); PMAPCOUNT(fixup_ref); rv = 1; @@ -4464,7 +4515,10 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va, * Turn off no-execute. */ KASSERT(opte & L2_XS_nG); - l2pte_set(ptep, opte & ~L2_XS_XN, opte); + l2pte_reset(ptep); + PTE_SYNC(ptep); + pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); + l2pte_set(ptep, opte & ~L2_XS_XN, 0); PTE_SYNC(ptep); rv = 1; PMAPCOUNT(fixup_exec); @@ -4481,6 +4535,7 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va, pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); if (*pdep != pde) { + /* XXXNH KASSERT *pdep == 0 ??? */ l1pte_setone(pdep, pde); PTE_SYNC(pdep); rv = 1; @@ -4612,9 +4667,6 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va, } #endif - pmap_tlb_flush_SE(pm, va, - (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); - rv = 1; out: @@ -4922,6 +4974,11 @@ pmap_update(pmap_t pm) } #ifdef ARM_MMU_EXTENDED +#if defined(MULTIPROCESSOR) + armreg_bpiallis_write(0); +#else + armreg_bpiall_write(0); +#endif #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); @@ -5733,6 +5790,8 @@ pmap_growkernel(vaddr_t maxkvaddr) | L1_C_DOM(PMAP_DOMAIN_KERNEL); #ifdef ARM_MMU_EXTENDED l1pte_setone(pdep, npde); + /* XXXNH ??? */ + PDE_SYNC(pdep); #else /* Distribute new L1 entry to all other L1s */ SLIST_FOREACH(l1, &l1_list, l1_link) { @@ -6618,6 +6677,9 @@ pmap_map_chunk(vaddr_t l1pt, vaddr_t va, #ifdef VERBOSE_INIT_ARM printf("sS"); #endif +#ifdef ARM_MMU_EXTENDED + KASSERT(!(npde & L1_S_V6_nG)); +#endif l1pte_set(&pdep[l1slot], npde); PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); va += L1_SS_SIZE; @@ -6640,6 +6702,9 @@ pmap_map_chunk(vaddr_t l1pt, vaddr_t va, #ifdef VERBOSE_INIT_ARM printf("S"); #endif +#ifdef ARM_MMU_EXTENDED + KASSERT(!(npde & L1_S_V6_nG)); +#endif l1pte_set(&pdep[l1slot], npde); PDE_SYNC(&pdep[l1slot]); va += L1_S_SIZE; @@ -6676,6 +6741,9 @@ pmap_map_chunk(vaddr_t l1pt, vaddr_t va, #ifdef VERBOSE_INIT_ARM printf("L"); #endif +#ifdef ARM_MMU_EXTENDED + KASSERT(!(npte & L2_XS_nG)); +#endif l2pte_set(ptep, npte, 0); PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); va += L2_L_SIZE; @@ -6696,6 +6764,9 @@ pmap_map_chunk(vaddr_t l1pt, vaddr_t va, | (va & 0x80000000 ? 0 : L2_XS_nG) #endif | L2_S_PROT(PTE_KERNEL, prot) | f2s; +#ifdef ARM_MMU_EXTENDED + KASSERT(!(npte & L2_XS_nG)); +#endif l2pte_set(ptep, npte, 0); PTE_SYNC(ptep); va += PAGE_SIZE; Index: sys/arch/arm/cortex/gic.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/cortex/gic.c,v retrieving revision 1.10 diff -u -p -r1.10 gic.c --- sys/arch/arm/cortex/gic.c 19 May 2014 22:47:53 -0000 1.10 +++ sys/arch/arm/cortex/gic.c 20 Oct 2014 18:39:54 -0000 @@ -29,6 +29,7 @@ */ #include "opt_ddb.h" +#include "opt_multiprocessor.h" #define _INTR_PRIVATE @@ -63,7 +64,10 @@ static void armgic_establish_irq(struct static void armgic_source_name(struct pic_softc *, int, char *, size_t); #endif +#undef MULTIPROCESSOR + #ifdef MULTIPROCESSOR +check static void armgic_cpu_init(struct pic_softc *, struct cpu_info *); static void armgic_ipi_send(struct pic_softc *, const kcpuset_t *, u_long); #endif Index: sys/arch/arm/include/mutex.h =================================================================== RCS file: /cvsroot/src/sys/arch/arm/include/mutex.h,v retrieving revision 1.18 diff -u -p -r1.18 mutex.h --- sys/arch/arm/include/mutex.h 12 Oct 2014 06:00:14 -0000 1.18 +++ sys/arch/arm/include/mutex.h 20 Oct 2014 18:39:54 -0000 @@ -32,6 +32,8 @@ #ifndef _ARM_MUTEX_H_ #define _ARM_MUTEX_H_ +#include "opt_multiprocessor.h" + /* * The ARM mutex implementation is troublesome, because pre-v6 ARM lacks a * compare-and-swap operation. However, there aren't any MP pre-v6 ARM Index: sys/arch/arm/include/rwlock.h =================================================================== RCS file: /cvsroot/src/sys/arch/arm/include/rwlock.h,v retrieving revision 1.8 diff -u -p -r1.8 rwlock.h --- sys/arch/arm/include/rwlock.h 12 Jun 2014 08:50:52 -0000 1.8 +++ sys/arch/arm/include/rwlock.h 20 Oct 2014 18:39:54 -0000 @@ -32,6 +32,8 @@ #ifndef _ARM_RWLOCK_H_ #define _ARM_RWLOCK_H_ +#include "opt_multiprocessor.h" + struct krwlock { volatile uintptr_t rw_owner; }; Index: sys/arch/arm/include/arm32/pmap.h =================================================================== RCS file: /cvsroot/src/sys/arch/arm/include/arm32/pmap.h,v retrieving revision 1.135 diff -u -p -r1.135 pmap.h --- sys/arch/arm/include/arm32/pmap.h 31 Jul 2014 08:04:57 -0000 1.135 +++ sys/arch/arm/include/arm32/pmap.h 20 Oct 2014 18:39:54 -0000 @@ -511,7 +511,7 @@ pmap_ptesync(pt_entry_t *ptep, size_t cn #endif } #if ARM_MMU_V7 > 0 - __asm("dsb"); + __asm __volatile("dsb" ::: "memory"); #endif } Index: sys/arch/arm/include/arm32/pte.h =================================================================== RCS file: /cvsroot/src/sys/arch/arm/include/arm32/pte.h,v retrieving revision 1.18 diff -u -p -r1.18 pte.h --- sys/arch/arm/include/arm32/pte.h 8 Aug 2014 07:47:24 -0000 1.18 +++ sys/arch/arm/include/arm32/pte.h 20 Oct 2014 18:39:54 -0000 @@ -304,34 +304,32 @@ typedef uint32_t pt_entry_t; /* L2 table /* * Type Extension bits for ARM V6 and V7 MMU * - * TEX C B Shared - * 000 0 0 Strong order yes - * 000 0 1 Shared device yes - * 000 1 0 write through, no write alloc S-bit - * 000 1 1 write back, no write alloc S-bit - * 001 0 0 non-cacheable S-bit + * TEX C B Shared + * 000 0 0 Strong order yes + * 000 0 1 Shared device yes + * 000 1 0 Outer and Inner write through, no write alloc S-bit + * 000 1 1 Outer and Inner write back, no write alloc S-bit + * 001 0 0 Outer and Inner non-cacheable S-bit * 001 0 1 reserved * 001 1 0 reserved - * 001 1 1 write back, write alloc S-bit - * 010 0 0 Non-shared device no + * 001 1 1 Outer and Inner write back, write alloc S-bit + * 010 0 0 Non-shared device no * 010 0 1 reserved * 010 1 X reserved * 011 X X reserved - * 1BB A A BB for internal, AA for external S-bit + * 1BB A A BB for inner, AA for outer S-bit * - * BB internal cache - * 0 0 Non-cacheable non-buffered - * 0 1 Write back, write alloc, buffered - * 1 0 Write through, no write alloc, buffered - * (non-cacheable for MPCore) - * 1 1 Write back, no write alloc, buffered - * (write back, write alloc for MPCore) + * BB inner cache + * 0 0 Non-cacheable + * 0 1 Write back, write alloc + * 1 0 Write through, no write alloc + * 1 1 Write back, no write alloc * - * AA external cache - * 0 0 Non-cacheable non-buffered - * 0 1 Write back, write alloc, buffered - * 1 0 Write through, no write alloc, buffered - * 1 1 Write back, no write alloc, buffered + * AA outer cache + * 0 0 Non-cacheable + * 0 1 Write back, write alloc + * 1 0 Write through, no write alloc + * 1 1 Write back, no write alloc */ #define TEX_ARMV6_TEX 0x07 /* 3 bits in TEX */ Index: sys/arch/arm/mainbus/cpu_mainbus.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/mainbus/cpu_mainbus.c,v retrieving revision 1.15 diff -u -p -r1.15 cpu_mainbus.c --- sys/arch/arm/mainbus/cpu_mainbus.c 5 Jun 2014 03:46:26 -0000 1.15 +++ sys/arch/arm/mainbus/cpu_mainbus.c 20 Oct 2014 18:39:54 -0000 @@ -46,6 +46,8 @@ #include __KERNEL_RCSID(0, "$NetBSD: cpu_mainbus.c,v 1.15 2014/06/05 03:46:26 matt Exp $"); +#include "opt_multiprocessor.h" + #include #include #include Index: sys/arch/arm/pic/pic.c =================================================================== RCS file: /cvsroot/src/sys/arch/arm/pic/pic.c,v retrieving revision 1.23 diff -u -p -r1.23 pic.c --- sys/arch/arm/pic/pic.c 13 Oct 2014 09:21:06 -0000 1.23 +++ sys/arch/arm/pic/pic.c 20 Oct 2014 18:39:54 -0000 @@ -30,6 +30,7 @@ #define _INTR_PRIVATE #include "opt_ddb.h" +#include "opt_multiprocessor.h" #include __KERNEL_RCSID(0, "$NetBSD: pic.c,v 1.23 2014/10/13 09:21:06 skrll Exp $"); @@ -593,7 +594,7 @@ pic_add(struct pic_softc *pic, int irqba KASSERT((slot == 0) == (pic->pic_ops->pic_set_priority != NULL)); #endif #ifdef MULTIPROCESSOR - KASSERT((slot == 0) == (pic->pic_ops->pic_ipi_send != NULL)); + //KASSERT((slot == 0) == (pic->pic_ops->pic_ipi_send != NULL)); #endif pic_list[slot] = pic; } Index: sys/arch/evbarm/awin/awin_start.S =================================================================== RCS file: /cvsroot/src/sys/arch/evbarm/awin/awin_start.S,v retrieving revision 1.3 diff -u -p -r1.3 awin_start.S --- sys/arch/evbarm/awin/awin_start.S 10 Oct 2014 23:51:28 -0000 1.3 +++ sys/arch/evbarm/awin/awin_start.S 20 Oct 2014 18:39:55 -0000 @@ -162,11 +162,13 @@ _C_LABEL(awin_start): lsr r1, r1, #16 // MP init based on SoC ID +#if 0 #if defined(ALLWINNER_A20) movw r0, #AWIN_SRAM_VER_KEY_A20 cmp r1, r0 bleq a20_mpinit #endif +#endif #if defined(ALLWINNER_A31) movw r0, #AWIN_SRAM_VER_KEY_A31 cmp r1, r0 Index: sys/arch/evbarm/conf/BPI =================================================================== RCS file: /cvsroot/src/sys/arch/evbarm/conf/BPI,v retrieving revision 1.4 diff -u -p -r1.4 BPI --- sys/arch/evbarm/conf/BPI 19 Oct 2014 15:27:32 -0000 1.4 +++ sys/arch/evbarm/conf/BPI 20 Oct 2014 18:39:55 -0000 @@ -19,13 +19,17 @@ options RTC_OFFSET=0 # hardware clock i no makeoptions BOARDTYPE makeoptions BOARDTYPE="bpi" -#options UVMHIST,UVMHIST_PRINT -options CPU_CORTEXA8 +options UVMHIST +#options UVMHIST_PRINT +#options CPU_CORTEXA8 options CPU_CORTEXA7 -options ALLWINNER_A10 +#options ALLWINNER_A10 options ALLWINNER_A20 options PMAPCOUNTERS options AWIN_CONSOLE_EARLY +#options MULTIPROCESSOR +#options ARM11_COMPAT_MMU - doesn't build + # Architecture options @@ -140,10 +144,11 @@ options BUFQ_PRIOCSCAN #options PERFCTRS # performance counters options DIAGNOSTIC # internal consistency checks -#options DEBUG +#options LOCKDEBUG +options DEBUG #options PMAP_DEBUG # Enable pmap_debug_level code #options IPKDB # remote kernel debugging -#options VERBOSE_INIT_ARM # verbose bootstraping messages +options VERBOSE_INIT_ARM # verbose bootstraping messages options DDB # in-kernel debugger options DDB_ONPANIC=1 options DDB_HISTORY_SIZE=100 # Enable history editing in DDB @@ -176,7 +181,7 @@ config netbsd root on ? type ? mainbus0 at root # The boot cpu -cpu* at mainbus? +cpu0 at mainbus? # Specify the memory size in megabytes (optional). #options MEMSIZE=256 @@ -297,11 +302,33 @@ awge0 at awinio0 port ? include "dev/usb/usbdevices.config" -midi* at midibus? +# MII/PHY support +exphy* at mii? phy ? # 3Com internal PHYs +gentbi* at mii? phy ? # Generic Ten-Bit 1000BASE-[CLS]X PHYs +glxtphy* at mii? phy ? # Level One LXT-1000 PHYs +gphyter* at mii? phy ? # NS83861 Gig-E PHY +icsphy* at mii? phy ? # Integrated Circuit Systems ICS189x +igphy* at mii? phy ? # Intel IGP01E1000 +ihphy* at mii? phy ? # Intel 82577 PHYs +ikphy* at mii? phy ? # Intel 82563 PHYs +inphy* at mii? phy ? # Intel 82555 PHYs +iophy* at mii? phy ? # Intel 82553 PHYs +lxtphy* at mii? phy ? # Level One LXT-970 PHYs +makphy* at mii? phy ? # Marvell Semiconductor 88E1000 PHYs +nsphy* at mii? phy ? # NS83840 PHYs +nsphyter* at mii? phy ? # NS83843 PHYs +pnaphy* at mii? phy ? # generic HomePNA PHYs +qsphy* at mii? phy ? # Quality Semiconductor QS6612 PHYs +rdcphy* at mii? phy ? # RDC R6040 10/100 PHY +rgephy* at mii? phy ? # Realtek 8169S/8110S internal PHYs +rlphy* at mii? phy ? # Realtek 8139/8201L PHYs +sqphy* at mii? phy ? # Seeq 80220/80221/80223 PHYs +tlphy* at mii? phy ? # ThunderLAN PHYs +tqphy* at mii? phy ? # TDK Semiconductor PHYs +urlphy* at mii? phy ? # Realtek RTL8150L internal PHYs +ukphy* at mii? phy ? # generic unknown PHYs -rlphy* at mii? phy ? -rgephy* at mii? phy ? -ukphy* at mii? phy ? +midi* at midibus? # Pseudo-Devices Index: sys/kern/kern_lock.c =================================================================== RCS file: /cvsroot/src/sys/kern/kern_lock.c,v retrieving revision 1.155 diff -u -p -r1.155 kern_lock.c --- sys/kern/kern_lock.c 14 Sep 2013 20:24:22 -0000 1.155 +++ sys/kern/kern_lock.c 20 Oct 2014 18:40:02 -0000 @@ -173,6 +173,10 @@ _kernel_lock(int nlocks) return; } + if (l->l_blcnt != 0) { +printf_nolog("%s: ci %p l %p l->l_blcnt %d\n", __func__, ci, l , l->l_blcnt); +printf_nolog("%s: curcpu %p curlwp %p curlwp->l_blcnt %d\n", __func__, curcpu(), curlwp , curlwp->l_blcnt); +} _KERNEL_LOCK_ASSERT(l->l_blcnt == 0); LOCKDEBUG_WANTLOCK(kernel_lock_dodebug, kernel_lock, RETURN_ADDRESS, 0); Index: sys/sys/userret.h =================================================================== RCS file: /cvsroot/src/sys/sys/userret.h,v retrieving revision 1.26 diff -u -p -r1.26 userret.h --- sys/sys/userret.h 7 Apr 2013 07:54:53 -0000 1.26 +++ sys/sys/userret.h 20 Oct 2014 18:40:04 -0000 @@ -79,7 +79,7 @@ mi_userret(struct lwp *l) struct cpu_info *ci; #endif - KASSERT(l->l_blcnt == 0); + KASSERTMSG(l->l_blcnt == 0, "l_blcnt %d ci_biglock_count %d", l->l_blcnt, curcpu()->ci_biglock_count); #ifndef __HAVE_PREEMPTION KASSERT(curcpu()->ci_biglock_count == 0); #endif