Index: sys/arch/mips/mips/locore_mips1.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/locore_mips1.S,v
retrieving revision 1.85
diff -u -p -r1.85 locore_mips1.S
--- sys/arch/mips/mips/locore_mips1.S	11 Jun 2015 07:30:10 -0000	1.85
+++ sys/arch/mips/mips/locore_mips1.S	4 Jul 2016 13:57:05 -0000
@@ -497,6 +497,7 @@ NESTED_NOPROFILE(MIPSX(kern_intr), KERNF
 	/*
 	 * Now we can enable interrupts since no interrupts can be delivered
 	 */
+	/* XXXNH - mipsX_subr.S leaves it alone */
 	mfc0	v1, MIPS_COP_0_STATUS
 	nop
 	or	v0, v1, MIPS_SR_INT_IE
@@ -544,9 +545,15 @@ NESTED_NOPROFILE(MIPSX(kern_intr), KERNF
 	beqz	v0, 4f				#   nope
 	 nop
 	xor	t0, v0				# clear preempt bit
+
 	INT_S	t0, CPU_INFO_SOFTINTS(s2)	# and save it.
+
+	jal	_C_LABEL(splx_noprof)		# drop to IPL_SCHED
+	 li	a0, IPL_SCHED
+
 	jal	_C_LABEL(kpreempt)		# kpreempt(pc)
-	 PTR_L	a0, TF_BASE+TF_REG_EPC(sp)
+	 li	a0, -2
+
 #endif /* __HAVE_PREEMPTION */
 4:
 #endif /* __HAVE_FAST_SOFTINT */
@@ -663,17 +670,19 @@ NESTED_NOPROFILE(MIPSX(user_gen_exceptio
 	move	MIPS_CURLWP, k1
 #ifdef NOFPU
 	li	t0, MIPS_SR_INT_IE		# reenable intrs
+	or	t0, a0
 #else
-	lui	t0, %hi(MIPS_SR_COP_1_BIT)
+	lui	t0, %hi(~MIPS_SR_COP_1_BIT)
+	addiu	t0, %lo(~MIPS_SR_COP_1_BIT)
 	and	t0, a0
 	or	t0, MIPS_SR_INT_IE		# make sure intrs are still on
 #endif
-	xor	t0, a0				# turn off the FPU & ints on
+	mtc0	t0, MIPS_COP_0_STATUS
+	nop
+
 /*
  * Call the trap handler.
  */
-	mtc0	t0, MIPS_COP_0_STATUS
-
 	jal	_C_LABEL(trap)
 	 REG_S	a3, CALLFRAME_RA(sp)		# for debugging
 /*
@@ -775,14 +784,16 @@ NESTED_NOPROFILE(MIPSX(user_intr), CALLF
 	 * interrupts since they all masked.
 	 */
 	mfc0	v1, MIPS_COP_0_STATUS
-#ifndef NOFPU
-	lui	v0, %hi(MIPS_SR_COP_1_BIT)
+#ifdef NOFPU
+	li	v0, MIPS_SR_INT_IE		# reenable intrs
+	or	v0, v1
+#else
+	lui	v0, %hi(~MIPS_SR_COP_1_BIT)
+	addiu	v0, %lo(~MIPS_SR_COP_1_BIT)
 	and	v0, v1
 	or	v0, MIPS_SR_INT_IE		# make sure intrs are still on
-#else
-	li	v0, MIPS_SR_INT_IE		# reenable intrs
 #endif
-	xor	v0, v1
+
 	mtc0	v0, MIPS_COP_0_STATUS
 	nop
 
@@ -867,11 +878,14 @@ NESTED_NOPROFILE(MIPSX(user_intr), CALLF
 	REG_S	s7, CALLFRAME_SIZ+TF_REG_S7(sp)	# $23
 	REG_S	s8, CALLFRAME_SIZ+TF_REG_S8(sp)	# $30
 
-	mfc0	t0, MIPS_COP_0_STATUS
-	PTR_LA	ra, MIPSX(user_return)		# load delay
+	mfc0	t0, MIPS_COP_0_STATUS		#
+	nop
 	or	t0, MIPS_SR_INT_IE		# enable interrupts
+	mtc0	t0, MIPS_COP_0_STATUS		# enable interrupts (spl0)
+	nop
+	PTR_LA	ra, MIPSX(user_return)
 	j	_C_LABEL(ast)			# ast()
-	 mtc0	t0, MIPS_COP_0_STATUS		# enable interrupts (spl0)
+	 nop
 	.set	at
 END(MIPSX(user_intr))
 
@@ -947,14 +961,16 @@ NESTED_NOPROFILE(MIPSX(systemcall), CALL
 	/*
 	 * Turn off FPU
 	 */
+/* XXXNH Current */
 #ifdef NOFPU
-	li	t0, MIPS_SR_INT_IE
+	li	t0, MIPS_SR_INT_IE		# reenable intrs
+	or	t0, a1
 #else
-	lui	t0, %hi(MIPS_SR_COP_1_BIT)
+	lui	t0, %hi(~MIPS_SR_COP_1_BIT)
+	addiu	t0, %lo(~MIPS_SR_COP_1_BIT)
 	and	t0, a1
 	ori	t0, MIPS_SR_INT_IE		# turn on IEc, enable intr.
 #endif
-	xor	t0, a1				# turns off the FPU & ints on
 	mtc0	t0, MIPS_COP_0_STATUS		# re-enable interrupts
 /*
  * Call the system call handler.