Index: sys/arch/mips/mips/genassym.cf
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/genassym.cf,v
retrieving revision 1.67
diff -u -p -r1.67 genassym.cf
--- sys/arch/mips/mips/genassym.cf	11 Jul 2016 16:15:36 -0000	1.67
+++ sys/arch/mips/mips/genassym.cf	8 Aug 2016 12:34:45 -0000
@@ -145,8 +145,10 @@ define	L_PROC			offsetof(struct lwp, l_p
 define	L_STAT			offsetof(struct lwp, l_stat)
 ifndef _MODULE
 define	L_MD_UTF		offsetof(struct lwp, l_md.md_utf)
+ifndef _LP64
 define	L_MD_UPTE_0		offsetof(struct lwp, l_md.md_upte[0])
 define	L_MD_UPTE_1		offsetof(struct lwp, l_md.md_upte[1])
+endif
 define	L_MD_ASTPENDING		offsetof(struct lwp, l_md.md_astpending)
 endif
 define	L_WCHAN			offsetof(struct lwp, l_wchan)
Index: sys/arch/mips/mips/mipsX_subr.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mipsX_subr.S,v
retrieving revision 1.84
diff -u -p -r1.84 mipsX_subr.S
--- sys/arch/mips/mips/mipsX_subr.S	8 Aug 2016 10:21:34 -0000	1.84
+++ sys/arch/mips/mips/mipsX_subr.S	8 Aug 2016 12:34:48 -0000
@@ -2714,13 +2714,18 @@ END(MIPSX(lwp_trampoline))
  * USPACE is already in another place of TLB before that, and make
  * sure TBIS(it) in the case.
  */
+
 LEAF_NOPROFILE(MIPSX(cpu_switch_resume))
-#if !defined(ENABLE_MIPS_16KB_PAGE) && !defined(ENABLE_MIPS_8KB_PAGE)
+#if !defined(_LP64)
 	INT_L	a1, L_MD_UPTE_0(a0)		# a1 = upte[0]
 #if (PGSHIFT & 1)
 	INT_ADD a2, a1, MIPS3_PG_NEXT		# a2 = upper half
 #else
+#if (USPACE > PAGE_SIZE)
 	INT_L	a2, L_MD_UPTE_1(a0)		# a2 = upte[1]
+#else
+	li	a2, MIPS3_PG_G			# a2 = invalid/global
+#endif
 #endif
 	PTR_L	v0, L_PCB(a0)			# va = l->l_addr
 #if VM_MIN_KERNEL_ADDRESS == MIPS_KSEG2_START
@@ -2785,7 +2790,7 @@ MIPSX(entry0set):
 	_MTC0	ta1, MIPS_COP_0_TLB_HI		# restore TLB_HI
 	COP0_SYNC
 MIPSX(resume):
-#endif /* !ENABLE_MIPS_16KB_PAGE */
+#endif /* !_LP64 */
 #ifdef MIPSNNR2
 	PTR_L	v0, L_PRIVATE(a0)		# get lwp private
 	_MTC0	v0, MIPS_COP_0_USERLOCAL	# make available for rdhwr
Index: sys/arch/mips/mips/vm_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/vm_machdep.c,v
retrieving revision 1.150
diff -u -p -r1.150 vm_machdep.c
--- sys/arch/mips/mips/vm_machdep.c	31 Jul 2016 15:33:42 -0000	1.150
+++ sys/arch/mips/mips/vm_machdep.c	8 Aug 2016 12:34:48 -0000
@@ -115,19 +114,28 @@ cpu_lwp_fork(struct lwp *l1, struct lwp 
 		tf->tf_regs[_R_SP] = (intptr_t)stack + stacksize;
 
 	l2->l_md.md_utf = tf;
-#if (USPACE > PAGE_SIZE)
+#if !defined(_LP64)
+ 	CTASSERT(__arraycount(l2->l_md.md_upte) >= UPAGES);
+	for (u_int i = 0; i < __arraycount(l2->l_md.md_upte); i++) {
+		l2->l_md.md_upte[i] = 0;
+	}
 	if (!pmap_md_direct_mapped_vaddr_p(ua2)) {
-		__CTASSERT((PGSHIFT & 1) || UPAGES % 2 == 0);
+printf("%s: ua2 %"PRIxVADDR"\n", __func__, ua2);
 		pt_entry_t * const pte = pmap_pte_lookup(pmap_kernel(), ua2);
 		const uint32_t x = MIPS_HAS_R4K_MMU
 		    ? (MIPS3_PG_RO | MIPS3_PG_WIRED)
 		    : 0;
-
 		for (u_int i = 0; i < UPAGES; i++) {
+			KASSERT(pte[i] & (MIPS_HAS_R4K_MMU ?
+			    MIPS3_PG_G : MIPS1_PG_G));
 			KASSERT(pte_valid_p(pte[i]));
 			l2->l_md.md_upte[i] = pte[i] & ~x;
+			KASSERT(l2->l_md.md_upte[i] & (MIPS_HAS_R4K_MMU ?
+			    MIPS3_PG_G : MIPS1_PG_G));
 		}
 	}
+#else
+	KASSERT(pmap_md_direct_mapped_vaddr_p(ua2));
 #endif
 	/*
 	 * Rig kernel stack so that it would start out in lwp_trampoline()
@@ -237,7 +245,7 @@ cpu_uarea_free(void *va)
 
 #ifdef MIPS3_PLUS
 	if (MIPS_CACHE_VIRTUAL_ALIAS)
-		mips_dcache_inv_range((vaddr_t)va, USPACE);
+		mips_dcache_inv_range((intptr_t)(vaddr_t)va, USPACE);
 #endif
 
 	for (const paddr_t epa = pa + USPACE; pa < epa; pa += PAGE_SIZE) {