Index: sys/arch/mips/mips/spl.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/spl.S,v
retrieving revision 1.19
diff -u -p -r1.19 spl.S
--- sys/arch/mips/mips/spl.S	9 Aug 2020 09:23:17 -0000	1.19
+++ sys/arch/mips/mips/spl.S	9 Aug 2020 09:28:13 -0000
@@ -80,6 +80,10 @@ _splraise:
 	or	v1, MIPS_INT_MASK		# enable all interrupts
 	xor	a0, v1				# disable ipl's masked bits
 	DYNAMIC_STATUS_MASK(a0,v0)		# machine dependent masking
+
+#if defined(MIPSNNR2)
+	di					# disable interrupts
+#else
 #if !defined(__mips_o32)
 	or	v1, MIPS_SR_INT_IE		#
 	xor	v1, MIPS_SR_INT_IE		# clear interrupt enable bit
@@ -88,6 +92,8 @@ _splraise:
 	mtc0	zero, MIPS_COP_0_STATUS		# disable interrupts
 #endif
 	COP0_SYNC
+#endif
+
 #ifdef MULTIPROCESSOR
 	PTR_L	a3, L_CPU(MIPS_CURLWP)		# make sure curcpu is correct
 	NOP_L					# load delay
@@ -137,6 +143,10 @@ STATIC_XLEAF(_splsw_splx_noprof)		# does
 	xor	a1, MIPS_INT_MASK		# invert SR bits
 	or	v1, a1				# set any bits for this IPL
 	DYNAMIC_STATUS_MASK(v1,t0)		# machine dependent masking
+
+#if defined(MIPSNNR2)
+	di					# disable interrupts
+#else
 #if !defined(__mips_o32)
 	or	v0, v1, MIPS_SR_INT_IE		#
 	xor	v0, MIPS_SR_INT_IE		# clear interrupt enable bit
@@ -145,6 +155,8 @@ STATIC_XLEAF(_splsw_splx_noprof)		# does
 	mtc0	zero, MIPS_COP_0_STATUS		# disable interrupts
 #endif
 	COP0_SYNC
+#endif
+
 	INT_S	a0, CPU_INFO_CPL(a3)		# save IPL in cpu_info (KSEG0)
 	mtc0	v1, MIPS_COP_0_STATUS		# store back
 	COP0_SYNC
@@ -178,6 +190,10 @@ STATIC_LEAF(_splsw_spl0)
 	MFC0_HAZARD				# load delay
 	or	v0, a0, v1
 	DYNAMIC_STATUS_MASK(v0,t0)		# machine dependent masking
+
+#if defined(MIPSNNR2)
+	di					# disable interrupts
+#else
 #if !defined(__mips_o32)
 	or	v1, v0, MIPS_SR_INT_IE		#
 	xor	v1, MIPS_SR_INT_IE		# clear interrupt enable bit
@@ -186,6 +202,7 @@ STATIC_LEAF(_splsw_spl0)
 	mtc0	zero, MIPS_COP_0_STATUS		# disable interrupts
 #endif
 	COP0_SYNC
+#endif
 #if IPL_NONE == 0
 	INT_S	zero, CPU_INFO_CPL(a3)		# set ipl to 0
 #else
@@ -196,8 +213,11 @@ STATIC_LEAF(_splsw_spl0)
 END(_splsw_spl0)
 
 STATIC_LEAF(_splsw_setsoftintr)
-	mfc0	v1, MIPS_COP_0_STATUS		# save status register
+#if defined(MIPSNNR2)
+	di
+#else
 #if !defined(__mips_o32)
+	mfc0	v1, MIPS_COP_0_STATUS		# save status register
 	MFC0_HAZARD				# load delay
 	or	v0, v1, MIPS_SR_INT_IE		#
 	xor	v0, MIPS_SR_INT_IE		# clear interrupt enable bit
@@ -206,16 +226,24 @@ STATIC_LEAF(_splsw_setsoftintr)
 	mtc0	zero, MIPS_COP_0_STATUS		# disable interrupts
 #endif
 	COP0_SYNC
+#endif
 	mfc0	v0, MIPS_COP_0_CAUSE		# fetch cause register
 	MFC0_HAZARD				# load delay
 	or	v0, v0, a0			# set soft intr. bits
 	mtc0	v0, MIPS_COP_0_CAUSE		# store back
 	COP0_SYNC
+#if defined(MIPSNNR2)
+	ei
+#else
 	mtc0	v1, MIPS_COP_0_STATUS		# enable interrupts
+#endif
 	JR_HB_RA				# return (clear hazards)
 END(_splsw_setsoftintr)
 
 STATIC_LEAF(_splsw_clrsoftintr)
+#if defined(MIPSNNR2)
+	di
+#else
 	mfc0	v1, MIPS_COP_0_STATUS		# save status register
 #if !defined(__mips_o32)
 	MFC0_HAZARD				# load delay
@@ -226,12 +254,17 @@ STATIC_LEAF(_splsw_clrsoftintr)
 	mtc0	zero, MIPS_COP_0_STATUS		# disable interrupts
 #endif
 	COP0_SYNC
+#endif
 	mfc0	v0, MIPS_COP_0_CAUSE		# fetch cause register
 	nor	a0, zero, a0			# bitwise inverse of A0
 	and	v0, v0, a0			# clear soft intr. bits
 	mtc0	v0, MIPS_COP_0_CAUSE		# store back
 	COP0_SYNC
+#if defined(MIPSNNR2)
+	ei
+#else
 	mtc0	v1, MIPS_COP_0_STATUS		# enable interrupts
+#endif
 	JR_HB_RA				# return (clear hazards)
 END(_splsw_clrsoftintr)