? sys/cscope.out
? sys/arch/evbmips/conf/ERLITE.MP
? sys/arch/evbmips/conf/ERLITE.UP
? sys/arch/evbmips/conf/ERLITE32
Index: sys/arch/cobalt/conf/GENERIC
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/conf/GENERIC,v
retrieving revision 1.168
diff -u -p -r1.168 GENERIC
--- sys/arch/cobalt/conf/GENERIC	16 Jun 2020 06:36:56 -0000	1.168
+++ sys/arch/cobalt/conf/GENERIC	17 Jul 2020 09:25:31 -0000
@@ -42,8 +42,22 @@ options 	SYSCTL_INCLUDE_DESCR	# Include 
 options 	BUFQ_PRIOCSCAN
 
 # Debugging options
+#options 	BUS_DMA_DEBUG
+options 	ENABLE_MIPS_16KB_PAGE
+#options 	ENABLE_MIPS_8KB_PAGE
+#options 	ENABLE_MIPS_4KB_PAGE
+#options 	VMFAULT_TRACE
+#options 	PMAP_FAULTINFO
+#options 	 __HAVE_CPU_UAREA_ROUTINES
+options 	UVMHIST
+#options 	UVMHIST_PRINT
+#options 	UVMHIST_SIZE=5000
+#options 	SYSCALL_DEBUG
+#options 	KERNHIST_DELAY=10
+#options 	KERNHIST_PRINT
 options 	DIAGNOSTIC	# extra kernel sanity checking
-#options 	DEBUG		# extra kernel debugging support
+options 	DEBUG		# extra kernel debugging support
+#options 	LOCKDEBUG
 options 	DDB		# kernel dynamic debugger
 #options 	DDB_HISTORY_SIZE=100 # enable history editing in DDB
 makeoptions	DEBUG="-g"	# compile full symbol table
Index: sys/arch/evbmips/cavium/machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/cavium/machdep.c,v
retrieving revision 1.18
diff -u -p -r1.18 machdep.c
--- sys/arch/evbmips/cavium/machdep.c	16 Jul 2020 11:49:37 -0000	1.18
+++ sys/arch/evbmips/cavium/machdep.c	17 Jul 2020 09:25:31 -0000
@@ -370,8 +370,11 @@ mach_init_memory(void)
 	physmem = btoc(octeon_btinfo.obt_dram_size * 1024 * 1024);
 
 #ifdef MULTIPROCESSOR
-	const u_int cores = mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM;
-	mem_clusters[0].start = cores * 4096;
+	//const u_int cores = mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM;
+	//KASSERTMSG(cores == 2, "cores %d", cores);
+	const u_int cores = 2;
+	mem_clusters[0].start += cores * PAGE_SIZE;
+	mem_clusters[0].size  -= cores * PAGE_SIZE;
 #endif
 
 	/*
Index: sys/arch/evbmips/conf/GDIUM
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/conf/GDIUM,v
retrieving revision 1.37
diff -u -p -r1.37 GDIUM
--- sys/arch/evbmips/conf/GDIUM	3 Jan 2020 03:44:42 -0000	1.37
+++ sys/arch/evbmips/conf/GDIUM	17 Jul 2020 09:25:31 -0000
@@ -39,10 +39,12 @@ makeoptions	DEBUG="-g"
 options 	KTRACE			# system call tracing support
 options 	MSGBUFSIZE=8192		# dmesg buffer size
 
+#options 	PCI_NETBSD_CONFIGURE
+
 ## UVM options.
 #options 	UVM_PAGE_TRKOWN
-#options 	UVMHIST
-#options 	UVMHIST_PRINT	# Loud!
+options 	UVMHIST
+options 	KERNHIST_PRINT	# Loud!
 
 #options 	SCSIVERBOSE		# human readable SCSI error messages
 #options 	PCMCIAVERBOSE		# verbose PCMCIA configuration messages
Index: sys/arch/evbmips/conf/LOONGSON
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/conf/LOONGSON,v
retrieving revision 1.43
diff -u -p -r1.43 LOONGSON
--- sys/arch/evbmips/conf/LOONGSON	3 Jan 2020 03:44:42 -0000	1.43
+++ sys/arch/evbmips/conf/LOONGSON	17 Jul 2020 09:25:31 -0000
@@ -26,6 +26,7 @@ options 	INCLUDE_CONFIG_FILE	# embed con
 
 maxusers	16
 
+options 	PCI_NETBSD_CONFIGURE
 # Standard system options
 options 	DDB			# in-kernel debugger
 #options 	DDB_ONPANIC=0		# don't enter debugger on panic
Index: sys/arch/evbmips/conf/MALTA
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/conf/MALTA,v
retrieving revision 1.101
diff -u -p -r1.101 MALTA
--- sys/arch/evbmips/conf/MALTA	4 May 2020 12:15:43 -0000	1.101
+++ sys/arch/evbmips/conf/MALTA	17 Jul 2020 09:25:31 -0000
@@ -29,6 +29,8 @@ options 	SYSVSHM		# System V shared memo
 options 	NTP		# network time protocol
 
 # Debugging options
+options 	UVMHIST
+#options 	KERNHIST_PRINT
 options 	DIAGNOSTIC	# extra kernel sanity checking
 #options 	DEBUG		# extra kernel debugging support
 #options 	SYSCALL_DEBUG	# symbolic syscall names
@@ -100,7 +102,7 @@ options 	INET		# Internet protocols
 
 # These options enable verbose messages for several subsystems.
 # Warning, these may compile large string tables into the kernel!
-#options 	PCI_NETBSD_CONFIGURE	# NetBSD configures the PCI bus
+options 	PCI_NETBSD_CONFIGURE	# NetBSD configures the PCI bus
 options 	PCIVERBOSE	# verbose PCI device autoconfig messages
 #options 	PCI_CONFIG_DUMP	# verbosely dump PCI config space
 #options 	SCSIVERBOSE	# human readable SCSI error messages
@@ -111,7 +113,7 @@ options 	MIIVERBOSE	# verbose PHY autoco
 #
 # Do this if your firmware (usually PMON and YAMON) doens't enable the IDE
 # channels for you (thus causing the NetBSD `pciide' driver to ignore them).
-options 	PCI_NETBSD_ENABLE_IDE=0x1
+#options 	PCI_NETBSD_ENABLE_IDE=0x1
 
 options 	NFS_BOOT_DHCP
 
Index: sys/arch/evbmips/conf/OCTEON
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/conf/OCTEON,v
retrieving revision 1.2
diff -u -p -r1.2 OCTEON
--- sys/arch/evbmips/conf/OCTEON	16 Jul 2020 11:49:37 -0000	1.2
+++ sys/arch/evbmips/conf/OCTEON	17 Jul 2020 09:25:31 -0000
@@ -31,9 +31,11 @@ options 	SYSVSEM		# System V semaphores
 options 	SYSVSHM		# System V shared memory
 options 	NTP		# network time protocol
 
+options 	MULTIPROCESSOR
+
 # Debugging options
 options 	DIAGNOSTIC	# extra kernel sanity checking
-#options 	DEBUG		# extra kernel debugging support
+options 	DEBUG		# extra kernel debugging support
 #options 	USERCONF	# userconf(4) support
 #options 	SYSCTL_INCLUDE_DESCR	# Include sysctl descriptions in kernel
 options 	DDB		# kernel dynamic debugger
Index: sys/arch/evbmips/conf/std.gdium
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/conf/std.gdium,v
retrieving revision 1.5
diff -u -p -r1.5 std.gdium
--- sys/arch/evbmips/conf/std.gdium	2 Aug 2011 16:12:44 -0000	1.5
+++ sys/arch/evbmips/conf/std.gdium	17 Jul 2020 09:25:31 -0000
@@ -4,7 +4,6 @@ machine evbmips mips
 include		"conf/std"	# MI standard options
 
 options 	MIPS3_ENABLE_CLOCK_INTR
-options 	ENABLE_MIPS_16KB_PAGE
 
 #options 	UVMHIST,UVMHIST_PRINT
 
Index: sys/arch/evbmips/conf/std.loongson
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/conf/std.loongson,v
retrieving revision 1.2
diff -u -p -r1.2 std.loongson
--- sys/arch/evbmips/conf/std.loongson	8 Aug 2017 12:22:21 -0000	1.2
+++ sys/arch/evbmips/conf/std.loongson	17 Jul 2020 09:25:31 -0000
@@ -4,7 +4,6 @@ machine evbmips mips
 include		"conf/std"	# MI standard options
 
 options 	MIPS3_ENABLE_CLOCK_INTR
-options 	ENABLE_MIPS_16KB_PAGE
 
 options 	PMON
 
Index: sys/arch/evbmips/evbmips/interrupt.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/evbmips/interrupt.c,v
retrieving revision 1.24
diff -u -p -r1.24 interrupt.c
--- sys/arch/evbmips/evbmips/interrupt.c	26 Aug 2016 15:45:47 -0000	1.24
+++ sys/arch/evbmips/evbmips/interrupt.c	17 Jul 2020 09:25:31 -0000
@@ -32,7 +32,10 @@
 #include <sys/cdefs.h>
 __KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.24 2016/08/26 15:45:47 skrll Exp $");
 
+#define __INTR_PRIVATE
+
 #include <sys/param.h>
+#include <mips/intr.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/intr.h>
@@ -63,9 +66,18 @@ cpu_intr(int ppl, vaddr_t pc, uint32_t s
 
 	ci->ci_data.cpu_nintr++;
 
-	while (ppl < (ipl = splintr(&pending))) {
+	uint32_t cause;
+	__asm volatile("mfc0 %0,$%1" : "=r"(cause) : "n"(MIPS_COP_0_CAUSE));
+
+ci->ci_lastcause = cause;
+ci->ci_lastipl = ipl = splintr(&pending);
+ci->ci_lastpending = pending;
+	while (ppl < ipl) {
 		KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
 		splx(ipl);	/* lower to interrupt level */
+		KASSERTMSG(!((mips_cp0_status_read() & MIPS_INT_MASK) & ipl_sr_map.sr_bits[ipl]),
+		    "status %"PRIx32" ipl_sr_map[%d] %"PRIx32"\n", mips_cp0_status_read(),
+		    ipl, ipl_sr_map.sr_bits[ipl]);
 		KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
 
 		KASSERTMSG(ci->ci_cpl == ipl,
@@ -84,7 +96,7 @@ cpu_intr(int ppl, vaddr_t pc, uint32_t s
 			KASSERTMSG(ipl == IPL_SCHED,
 			    "%s: ipl (%d) != IPL_SCHED (%d)",
 			     __func__, ipl, IPL_SCHED);
-			/* call the common MIPS3 clock interrupt handler */ 
+			/* call the common MIPS3 clock interrupt handler */
 			mips3_clockintr(&cf);
 			pending ^= MIPS_INT_MASK_5;
 		}
@@ -105,8 +117,43 @@ cpu_intr(int ppl, vaddr_t pc, uint32_t s
 		 * to ppl.
 		 */
 		(void) splhigh();	/* disable interrupts */
+ci->ci_lastipl = ipl = splintr(&pending);
+ci->ci_lastpending = pending;
+
 	}
 
 	KASSERT(ci->ci_cpl == IPL_HIGH);
 	KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
 }
+
+
+extern	struct ipl_sr_map ipl_sr_map;
+
+int nh_splsw_splintr(uint32_t *);
+int
+nh_splsw_splintr(uint32_t *pendp)
+{
+	uint32_t cause;
+	uint32_t pending;
+
+	__asm volatile("mfc0 %0,$%1" : "=r"(cause) : "n"(MIPS_COP_0_STATUS));
+
+	pending = cause & MIPS_INT_MASK;
+
+	if (pending == 0)
+		goto out;
+
+	for (int ipl = IPL_VM; ipl <= IPL_HIGH; ipl++) {
+		uint32_t block = ipl_sr_map.sr_bits[ipl];
+		uint32_t allowed = block ^ MIPS_INT_MASK;
+		uint32_t p = pending & allowed;
+		if (p) {
+			*pendp = p;
+			return ipl;
+		}
+	}
+out:
+	*pendp = 0;
+	return IPL_NONE;
+}
+
Index: sys/arch/hpcmips/conf/GENERIC
===================================================================
RCS file: /cvsroot/src/sys/arch/hpcmips/conf/GENERIC,v
retrieving revision 1.242
diff -u -p -r1.242 GENERIC
--- sys/arch/hpcmips/conf/GENERIC	16 May 2020 13:46:11 -0000	1.242
+++ sys/arch/hpcmips/conf/GENERIC	17 Jul 2020 09:25:32 -0000
@@ -48,14 +48,18 @@ options 	DDB			# in-kernel debugger
 options 	DDB_HISTORY_SIZE=512	# enable history editing in DDB
 #options 	KGDB			# remote debugger
 #options 	DIAGNOSTIC		# extra kernel debugging checks
-#options 	DEBUG			# extra kernel debugging support
+options 	DEBUG			# extra kernel debugging support
+#options 	VMFAULT_TRACE
+#options 	PMAP_FAULTINFO
+options 	CACHE_DEBUG
 options 	KTRACE			# system call tracing support
 options 	MSGBUFSIZE=8192		# dmesg buffer size
 
 ## UVM options.
 #options 	UVM_PAGE_TRKOWN
-#options 	UVMHIST
+options 	UVMHIST
 #options 	UVMHIST_PRINT	# Loud!
+options 	KERNHIST_DELAY=0
 
 #options 	SCSIVERBOSE		# human readable SCSI error messages
 #options 	PCMCIAVERBOSE		# verbose PCMCIA configuration messages
Index: sys/arch/hpcmips/conf/VR41XX
===================================================================
RCS file: /cvsroot/src/sys/arch/hpcmips/conf/VR41XX,v
retrieving revision 1.75
diff -u -p -r1.75 VR41XX
--- sys/arch/hpcmips/conf/VR41XX	16 May 2020 13:46:11 -0000	1.75
+++ sys/arch/hpcmips/conf/VR41XX	17 Jul 2020 09:25:32 -0000
@@ -453,7 +453,7 @@ scsibus* at umass? channel ?
 uaudio*	at uhub? port ? configuration ?
 
 # USB MIDI
-umidi* at uhub? port ? configuration ?
+#umidi* at uhub? port ? configuration ?
 
 # USB IrDA bridges
 #uirda* at uhub? port ? configuration ? interface ?
Index: sys/arch/mips/cavium/octeon_cpunode.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/cavium/octeon_cpunode.c,v
retrieving revision 1.13
diff -u -p -r1.13 octeon_cpunode.c
--- sys/arch/mips/cavium/octeon_cpunode.c	23 Jun 2020 05:14:18 -0000	1.13
+++ sys/arch/mips/cavium/octeon_cpunode.c	17 Jul 2020 09:25:32 -0000
@@ -98,7 +98,7 @@ cpunode_mainbus_print(void *aux, const c
 int
 cpunode_mainbus_match(device_t parent, cfdata_t cf, void *aux)
 {
-	
+
 	return 1;
 }
 
@@ -182,6 +182,7 @@ octeon_fixup_cpu_info_references(int32_t
 	new_insns[1] &= __BITS(31,16);
 	new_insns[0] |= (uint16_t)((load_addr + 0x8000) >> 16);
 	new_insns[1] |= (uint16_t)load_addr;
+#define DEBUG_VERBOSE
 #ifdef DEBUG_VERBOSE
 	printf("%s: %08x: insn#1 %08x: lui r%u, %d\n",
 	    __func__, load_addr, new_insns[0],
@@ -272,6 +273,7 @@ cpu_cpunode_attach_common(device_t self,
 	}
 	cpu_attach_common(self, ci);
 #ifdef MULTIPROCESSOR
+	KASSERT(cpu_infos[cpu_index(ci)] == ci);
 	KASSERT(cpuid_infos[ci->ci_cpuid] == ci);
 #endif
 }
@@ -283,6 +285,10 @@ cpu_cpunode_attach(device_t parent, devi
 	const int cpunum = cnaa->cnaa_cpunum;
 
 	if (cpunum == 0) {
+struct cpu_info *ci = curcpu();
+printf("cpu%d: ci->ci_lastcause   %p\n", cpu_index(ci), &ci->ci_lastcause);
+printf("cpu%d: ci->ci_lastpending %p\n", cpu_index(ci), &ci->ci_lastpending);
+printf("cpu%d: ci->ci_lastipl     %p\n", cpu_index(ci), &ci->ci_lastipl);
 		cpu_cpunode_attach_common(self, curcpu());
 #ifdef MULTIPROCESSOR
 		mips_locoresw.lsw_cpu_init = octeon_cpu_init;
@@ -304,6 +310,10 @@ cpu_cpunode_attach(device_t parent, devi
 
 	cpu_cpunode_attach_common(self, ci);
 
+printf("cpu%d: ci->ci_lastcause   %p\n", cpu_index(ci), &ci->ci_lastcause);
+printf("cpu%d: ci->ci_lastpending %p\n", cpu_index(ci), &ci->ci_lastpending);
+printf("cpu%d: ci->ci_lastipl     %p\n", cpu_index(ci), &ci->ci_lastipl);
+
 	KASSERT(ci->ci_data.cpu_idlelwp != NULL);
 	for (int i = 0; i < 100 && !kcpuset_isset(cpus_hatched, cpunum); i++) {
 		delay(10000);
Index: sys/arch/mips/cavium/octeon_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/cavium/octeon_intr.c,v
retrieving revision 1.14
diff -u -p -r1.14 octeon_intr.c
--- sys/arch/mips/cavium/octeon_intr.c	23 Jun 2020 05:14:39 -0000	1.14
+++ sys/arch/mips/cavium/octeon_intr.c	17 Jul 2020 09:25:33 -0000
@@ -174,6 +174,9 @@ struct octeon_intrhand ipi_intrhands[2] 
 };
 #endif
 
+/*
+ * Need the top bit to be not blocked by IPL_HIGH???
+ */
 struct octeon_intrhand *octciu_intrs[NIRQS] = {
 #ifdef MULTIPROCESSOR
 	[CIU_INT_MBOX_15_0] = &ipi_intrhands[0],
@@ -308,7 +311,6 @@ octeon_intr_init(struct cpu_info *ci)
 	const char * const xname = cpu_name(ci);
 	struct cpu_softc *cpu = ci->ci_softc;
 
-
 	if (ci->ci_cpuid == 0) {
 		KASSERT(ci->ci_softc == &octeon_cpu0_softc);
 		ipl_sr_map = octeon_ipl_sr_map;
@@ -332,6 +334,10 @@ octeon_intr_init(struct cpu_info *ci)
 	cpu->cpu_int2_enable0 |= __BIT(CIU_INT_MBOX_31_16);
 #endif
 
+	printf(
+	    "cpu%d: enabling intr masks %#"PRIx64"/%#"PRIx64"/%#"PRIx64"\n",
+	    cpunum, cpu->cpu_int0_enable0, cpu->cpu_int1_enable0, cpu->cpu_int2_enable0);
+
 	if (ci->ci_dev)
 		aprint_verbose_dev(ci->ci_dev,
 		    "enabling intr masks %#"PRIx64"/%#"PRIx64"/%#"PRIx64"\n",
@@ -417,6 +423,14 @@ octeon_intr_establish(int irq, int ipl, 
 	struct cpu_softc * const cpu1 = &octeon_cpu1_softc;
 #endif
 
+	printf(
+	    "cpu%d: before intr masks %#"PRIx64"/%#"PRIx64"/%#"PRIx64"\n",
+	    0, cpu0->cpu_int0_enable0, cpu0->cpu_int1_enable0, cpu0->cpu_int2_enable0);
+#ifdef MULTIPROCESSOR
+	printf(
+	    "cpu%d: before intr masks %#"PRIx64"/%#"PRIx64"/%#"PRIx64"\n",
+	    1, cpu1->cpu_int0_enable0, cpu1->cpu_int1_enable0, cpu1->cpu_int2_enable0);
+#endif
 	switch (ipl) {
 	case IPL_VM:
 		cpu0->cpu_int0_enable0 |= irq_mask;
@@ -436,12 +450,22 @@ octeon_intr_establish(int irq, int ipl, 
 	case IPL_HIGH:
 		cpu0->cpu_int2_enable0 |= irq_mask;
 		mips3_sd(cpu0->cpu_int2_en0, cpu0->cpu_int2_enable0);
+#if 0
 #ifdef MULTIPROCESSOR
 		cpu1->cpu_int2_enable0 = cpu0->cpu_int2_enable0;
 		mips3_sd(cpu1->cpu_int2_en0, cpu1->cpu_int2_enable0);
 #endif
+#endif
 		break;
 	}
+	printf(
+	    "cpu%d: before intr masks %#"PRIx64"/%#"PRIx64"/%#"PRIx64"\n",
+	    0, cpu0->cpu_int0_enable0, cpu0->cpu_int1_enable0, cpu0->cpu_int2_enable0);
+#ifdef MULTIPROCESSOR
+	printf(
+	    "cpu%d: before intr masks %#"PRIx64"/%#"PRIx64"/%#"PRIx64"\n",
+	    1, cpu1->cpu_int0_enable0, cpu1->cpu_int1_enable0, cpu1->cpu_int2_enable0);
+#endif
 
 	mutex_exit(&octeon_intr_lock);
 
@@ -532,6 +556,9 @@ octeon_iointr(int ipl, vaddr_t pc, uint3
 		struct octeon_intrhand * const ih = octciu_intrs[irq];
 		cpu->cpu_intr_evs[irq].ev_count++;
 		if (__predict_true(ih != NULL)) {
+			KASSERTMSG(ih->ih_ipl <= ipl, "ih_ipl %d > ipl %d"
+			    "(ih %p pending %#"PRIx32")", ih->ih_ipl, ipl, ih,
+			    ipending);
 #ifdef MULTIPROCESSOR
 			if (ipl == IPL_VM) {
 				KERNEL_LOCK(1, NULL);
@@ -559,7 +586,9 @@ octeon_ipi_intr(void *arg)
 	struct cpu_softc * const cpu = ci->ci_softc;
 	uint32_t ipi_mask = (uintptr_t) arg;
 
-	KASSERTMSG((ipi_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED,
+	KASSERTMSG(
+	    ((ipi_mask & __BITS(31,16)) != 0 && ci->ci_cpl >= IPL_HIGH) !=
+	    ((ipi_mask & __BITS(15,0)) != 0 && ci->ci_cpl >= IPL_SCHED),
 	    "ipi_mask %#"PRIx32" cpl %d", ipi_mask, ci->ci_cpl);
 
 	ipi_mask &= mips3_ld(cpu->cpu_mbox_set);
Index: sys/arch/mips/include/cpu.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/cpu.h,v
retrieving revision 1.128
diff -u -p -r1.128 cpu.h
--- sys/arch/mips/include/cpu.h	1 Dec 2019 15:34:44 -0000	1.128
+++ sys/arch/mips/include/cpu.h	17 Jul 2020 09:25:33 -0000
@@ -101,6 +101,11 @@ struct cpu_info {
 	int ci_mtx_oldspl;		/* saved SPL value */
 	int ci_idepth;			/* hardware interrupt depth */
 	int ci_cpl;			/* current [interrupt] priority level */
+
+	uint32_t ci_lastcause;
+	uint32_t ci_lastpending;
+	uint32_t ci_lastipl;
+
 	uint32_t ci_next_cp0_clk_intr;	/* for hard clock intr scheduling */
 	struct evcnt ci_ev_count_compare;		/* hard clock intr counter */
 	struct evcnt ci_ev_count_compare_missed;	/* hard clock miss counter */
Index: sys/arch/mips/include/intr.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/intr.h,v
retrieving revision 1.10
diff -u -p -r1.10 intr.h
--- sys/arch/mips/include/intr.h	6 Jun 2015 04:31:52 -0000	1.10
+++ sys/arch/mips/include/intr.h	17 Jul 2020 09:25:33 -0000
@@ -112,10 +112,12 @@ typedef struct {
 
 #ifdef _KERNEL
 
+#if 0
 #if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS)
 #define __HAVE_PREEMPTION	1
 #define SOFTINT_KPREEMPT	(SOFTINT_COUNT+0)
 #endif
+#endif
 
 #ifdef __INTR_PRIVATE
 extern	struct splsw	mips_splsw;
Index: sys/arch/mips/include/mips_param.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/mips_param.h,v
retrieving revision 1.40
diff -u -p -r1.40 mips_param.h
--- sys/arch/mips/include/mips_param.h	19 Jun 2019 09:55:27 -0000	1.40
+++ sys/arch/mips/include/mips_param.h	17 Jul 2020 09:25:33 -0000
@@ -80,6 +80,10 @@
 #define MSGBUFSIZE	NBPG		/* default message buffer size */
 #endif
 
+#ifdef MIPS64_OCTEON
+#define COHERENCY_UNIT	128
+#define CACHE_LINE_SIZE	128
+#endif
 #ifndef COHERENCY_UNIT
 #define COHERENCY_UNIT	32	/* MIPS cachelines are usually 32 bytes */
 #endif
Index: sys/arch/mips/include/psl.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/psl.h,v
retrieving revision 1.19
diff -u -p -r1.19 psl.h
--- sys/arch/mips/include/psl.h	30 Jul 2016 06:27:45 -0000	1.19
+++ sys/arch/mips/include/psl.h	17 Jul 2020 09:25:33 -0000
@@ -60,6 +60,9 @@
 	 MIPS3_SR_EXL |		\
 	 MIPS3_INT_MASK)
 
+#define	MIPS3_PSL_IE 		\
+	(MIPS_SR_INT_IE)
+
 #define	MIPS3_USERMODE(ps) \
 	(((ps) & MIPS3_SR_KSU_MASK) == MIPS3_SR_KSU_USER)
 
@@ -75,6 +78,11 @@
 	 MIPS1_SR_INT_ENA_PREV |\
 	 MIPS_INT_MASK)
 
+#define	MIPS1_PSL_IE		\
+	(MIPS1_SR_INT_ENA_OLD |	\
+	 MIPS1_SR_INT_ENA_PREV |\
+	 MIPS_SR_INT_IE)
+
 #define	MIPS1_USERMODE(ps) \
 	((ps) & MIPS1_SR_KU_PREV)
 
@@ -84,6 +92,7 @@
 
 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* mips3 or greater only */
 # define  PSL_LOWIPL	MIPS3_PSL_LOWIPL
+# define  PSL_IE	MIPS3_PSL_IE
 # define  PSL_USERSET	MIPS3_PSL_USERSET
 # define  USERMODE(ps)	MIPS3_USERMODE(ps)
 #endif /* mips3 only */
@@ -91,6 +100,7 @@
 
 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* mips1 only */
 # define  PSL_LOWIPL	MIPS1_PSL_LOWIPL
+# define  PSL_IE	MIPS1_PSL_IE
 # define  PSL_USERSET	MIPS1_PSL_USERSET
 # define  USERMODE(ps)	MIPS1_USERMODE(ps)
 #endif /* mips1 only */
@@ -98,6 +108,7 @@
 
 #if  MIPS3_PLUS +  MIPS1 > 1
 # define PSL_LOWIPL	(CPUISMIPS3 ? MIPS3_PSL_LOWIPL : MIPS1_PSL_LOWIPL)
+# define PSL_IE		(CPUISMIPS3 ? MIPS3_PSL_IE : MIPS1_PSL_IE)
 # define PSL_USERSET	(CPUISMIPS3 ? MIPS3_PSL_USERSET : MIPS1_PSL_USERSET)
 # define USERMODE(ps)	(CPUISMIPS3 ? MIPS3_USERMODE(ps) : MIPS1_USERMODE(ps))
 #endif
Index: sys/arch/mips/include/types.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/types.h,v
retrieving revision 1.70
diff -u -p -r1.70 types.h
--- sys/arch/mips/include/types.h	30 Apr 2020 20:48:10 -0000	1.70
+++ sys/arch/mips/include/types.h	17 Jul 2020 09:25:33 -0000
@@ -146,7 +146,9 @@ typedef __uint32_t tlb_asid_t;
 #define	__SIMPLELOCK_LOCKED	1
 #define	__SIMPLELOCK_UNLOCKED	0
 
+#if 0
 #define	__HAVE_FAST_SOFTINTS
+#endif
 #define	__HAVE_SYSCALL_INTERN
 #define	__HAVE_CPU_LWP_SETPRIVATE
 #define	__HAVE_CPU_DATA_FIRST
Index: sys/arch/mips/ingenic/ingenic_regs.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/ingenic/ingenic_regs.h,v
retrieving revision 1.25
diff -u -p -r1.25 ingenic_regs.h
--- sys/arch/mips/ingenic/ingenic_regs.h	21 May 2017 06:49:13 -0000	1.25
+++ sys/arch/mips/ingenic/ingenic_regs.h	17 Jul 2020 09:25:33 -0000
@@ -118,7 +118,7 @@
 static inline void
 writereg(uint32_t reg, uint32_t val)
 {
-	*(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg) = val;
+	*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(reg) = val;
 	wbflush();
 }
 
@@ -126,7 +126,7 @@ static inline uint32_t
 readreg(uint32_t reg)
 {
 	wbflush();
-	return *(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg);
+	return *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(reg);
 }
 
 
@@ -395,6 +395,7 @@ readreg(uint32_t reg)
 #define JZ_GPIO_DRVHS	0x000000a4	/* drive high set register */
 #define JZ_GPIO_DRVHC	0x000000a8	/* drive high clear register */
 
+#if 1
 static inline void
 gpio_as_output(uint32_t g, int pin)
 {
@@ -503,6 +504,7 @@ gpio_as_input(uint32_t g, int pin)
 	writereg(reg + JZ_GPIO_PAT1S, mask);	/* use as input */
 	writereg(reg + JZ_GPIO_FLAGC, mask);	/* clear it just in case */
 }
+#endif
 
 /* I2C / SMBus */
 #define JZ_SMB0_BASE	0x10050000
Index: sys/arch/mips/mips/cpu_subr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/cpu_subr.c,v
retrieving revision 1.48
diff -u -p -r1.48 cpu_subr.c
--- sys/arch/mips/mips/cpu_subr.c	14 Jun 2020 06:50:31 -0000	1.48
+++ sys/arch/mips/mips/cpu_subr.c	17 Jul 2020 09:25:33 -0000
@@ -124,10 +124,11 @@ cpu_info_alloc(struct pmap_tlb_info *ti,
 	KASSERT(cpu_id < MAXCPUS);
 
 #ifdef MIPS64_OCTEON
-	vaddr_t exc_page = MIPS_UTLB_MISS_EXC_VEC + 0x1000*cpu_id;
-	__CTASSERT(sizeof(struct cpu_info) + sizeof(struct pmap_tlb_info) <= 0x1000 - 0x280);
+	KASSERT(cpu_id == 1);
+	vaddr_t exc_page = MIPS_UTLB_MISS_EXC_VEC + PAGE_SIZE*cpu_id;
+	__CTASSERT(sizeof(struct cpu_info) + sizeof(struct pmap_tlb_info) <= PAGE_SIZE - 0x280);
 
-	struct cpu_info * const ci = ((struct cpu_info *)(exc_page + 0x1000)) - 1;
+	struct cpu_info * const ci = ((struct cpu_info *)(exc_page + PAGE_SIZE)) - 1;
 	memset((void *)exc_page, 0, PAGE_SIZE);
 
 	if (ti == NULL) {
Index: sys/arch/mips/mips/db_interface.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/db_interface.c,v
retrieving revision 1.85
diff -u -p -r1.85 db_interface.c
--- sys/arch/mips/mips/db_interface.c	13 Jul 2020 12:56:58 -0000	1.85
+++ sys/arch/mips/mips/db_interface.c	17 Jul 2020 09:25:33 -0000
@@ -85,7 +85,9 @@ static void db_mach_cpu_cmd(db_expr_t, b
 
 void db_tlbdump_cmd(db_expr_t, bool, db_expr_t, const char *);
 void db_kvtophys_cmd(db_expr_t, bool, db_expr_t, const char *);
+void db_show_frame_cmd(db_expr_t, bool, db_expr_t, const char *);
 void db_cp0dump_cmd(db_expr_t, bool, db_expr_t, const char *);
+
 #ifdef MIPS64_XLS
 void db_mfcr_cmd(db_expr_t, bool, db_expr_t, const char *);
 void db_mtcr_cmd(db_expr_t, bool, db_expr_t, const char *);
@@ -532,6 +534,30 @@ db_cp0dump_cmd(db_expr_t addr, bool have
 	}
 }
 
+void
+db_show_frame_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
+{
+	struct trapframe *frame;
+
+	if (!have_addr) {
+		db_printf("frame address must be specified\n");
+		return;
+	}
+
+	frame = (struct trapframe *)addr;
+
+	db_printf("frame address = %p  ", frame);
+
+        for (size_t i = 0; i < 32; i += 4) {
+		db_printf(
+		    "[%2zu]=%08"PRIxREGISTER" [%2zu]=%08"PRIxREGISTER
+		    " [%2zu]=%08"PRIxREGISTER" [%2zu]=%08"PRIxREGISTER "\n",
+ 		    i + 0, frame->tf_regs[i + 0], i + 1, frame->tf_regs[i + 1],
+                    i + 2, frame->tf_regs[i + 2], i + 3, frame->tf_regs[i + 3]);
+        }
+}
+
+
 #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
 static void
 db_watch_cmd(db_expr_t address, bool have_addr, db_expr_t count,
@@ -698,7 +724,7 @@ db_mfcr_cmd(db_expr_t addr, bool have_ad
 		"mfcr %0,%1			\n\t"			\
 		".set pop 			\n\t"			\
 	    : "=r"(value) : "r"(addr));
-	
+
 	db_printf("control reg 0x%" DDB_EXPR_FMT "x = 0x%" PRIx64 "\n",
 	    addr, value);
 }
@@ -745,7 +771,7 @@ db_mach_nmi_cmd(db_expr_t addr, bool hav
 {
 	CPU_INFO_ITERATOR cii;
 	struct cpu_info *ci;
-	
+
 	if (!have_addr) {
 		db_printf("CPU not specific\n");
 		return;
@@ -784,11 +810,16 @@ db_mach_reset_cmd(db_expr_t addr, bool h
 const struct db_command db_machine_command_table[] = {
 #ifdef MULTIPROCESSOR
 	{ DDB_ADD_CMD("cpu",	db_mach_cpu_cmd,	0,
-	  "switch to another cpu", "cpu#", NULL) },
+		"switch to another cpu", "cpu#", NULL) },
 #endif
 	{ DDB_ADD_CMD("cp0",	db_cp0dump_cmd,	0,
 		"Dump CP0 registers.",
 		NULL, NULL) },
+	{ DDB_ADD_CMD("frame",	db_show_frame_cmd,	0,
+		"Displays the contents of a trapframe",
+		"[address]",
+		"   address:\taddress of trapfame to display")},
+
 #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
 	{ DDB_ADD_CMD("watch",	db_watch_cmd,		CS_MORE,
 		"set cp0 watchpoint",
@@ -799,7 +830,7 @@ const struct db_command db_machine_comma
 #endif	/* (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */
 	{ DDB_ADD_CMD("kvtop",	db_kvtophys_cmd,	0,
 		"Print the physical address for a given kernel virtual address",
-		"address", 
+		"address",
 		"   address:\tvirtual address to look up") },
 	{ DDB_ADD_CMD("tlb",	db_tlbdump_cmd,		0,
 		"Print out TLB entries. (only works with options DEBUG)",
@@ -987,7 +1018,7 @@ next_instr_address(db_addr_t pc, bool bd
 
 	if (bd == false)
 		return (pc + 4);
-	
+
 	if (pc < MIPS_KSEG0_START)
 		ins = mips_ufetch32((void *)pc);
 	else
@@ -1001,15 +1032,15 @@ next_instr_address(db_addr_t pc, bool bd
 
 #ifdef MULTIPROCESSOR
 
-bool 
+bool
 ddb_running_on_this_cpu_p(void)
-{               
+{
 	return ddb_cpu == cpu_number();
 }
 
-bool 
+bool
 ddb_running_on_any_cpu_p(void)
-{               
+{
 	return ddb_cpu != NOCPU;
 }
 
@@ -1027,7 +1058,7 @@ db_mach_cpu_cmd(db_expr_t addr, bool hav
 {
 	CPU_INFO_ITERATOR cii;
 	struct cpu_info *ci;
-	
+
 	if (!have_addr) {
 		cpu_debug_dump();
 		return;
Index: sys/arch/mips/mips/genassym.cf
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/genassym.cf,v
retrieving revision 1.69
diff -u -p -r1.69 genassym.cf
--- sys/arch/mips/mips/genassym.cf	20 Feb 2020 08:27:39 -0000	1.69
+++ sys/arch/mips/mips/genassym.cf	17 Jul 2020 09:25:33 -0000
@@ -160,6 +160,7 @@ define	VM_MIN_KERNEL_ADDRESS	VM_MIN_KERN
 define	VM_MAX_KERNEL_ADDRESS	VM_MAX_KERNEL_ADDRESS
 
 define	CI_NINTR		offsetof(struct cpu_info, ci_data.cpu_nintr)
+define	CI_WANT_RESCHED		offsetof(struct cpu_info, ci_want_resched)
 
 #				/* XXX */
 define	MIPSX_FLUSHICACHE	0
Index: sys/arch/mips/mips/lock_stubs_llsc.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/lock_stubs_llsc.S,v
retrieving revision 1.9
diff -u -p -r1.9 lock_stubs_llsc.S
--- sys/arch/mips/mips/lock_stubs_llsc.S	6 Apr 2019 03:06:26 -0000	1.9
+++ sys/arch/mips/mips/lock_stubs_llsc.S	17 Jul 2020 09:25:33 -0000
@@ -187,13 +187,13 @@ END(llsc_ucaserr)
  * void	mutex_enter(kmutex_t *mtx);
  */
 STATIC_LEAF(llsc_mutex_enter)
-	PTR_LL	t0, MTX_OWNER(a0)
 1:
+	PTR_LL	t0, MTX_OWNER(a0)
 	bnez	t0, 2f
 	 move	t2, MIPS_CURLWP
 	PTR_SC	t2, MTX_OWNER(a0)
 	beqz	t2, 1b
-	 PTR_LL	t0, MTX_OWNER(a0)
+	 nop
 	j	ra
 	 BDSYNC
 2:
@@ -225,9 +225,9 @@ END(llsc_mutex_exit)
  */
 STATIC_NESTED(llsc_mutex_spin_enter, CALLFRAME_SIZ, ra)
 	move	t0, a0
-	PTR_L	t2, L_CPU(MIPS_CURLWP)
 	INT_L	a0, MTX_IPL(t0)
 #ifdef PARANOIA
+	PTR_L	t2, L_CPU(MIPS_CURLWP)
 	INT_L	ta1, CPU_INFO_CPL(t2)
 #endif
 
@@ -245,6 +245,7 @@ STATIC_NESTED(llsc_mutex_spin_enter, CAL
 	 nop
 #endif /* PARANOIA */
 
+	PTR_L	t2, L_CPU(MIPS_CURLWP)
 	/*
 	 * If this is the first lock of the mutex, store the previous IPL for
 	 * exit.  Even if an interrupt happens, the mutex count will not change.
Index: sys/arch/mips/mips/locore.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/locore.S,v
retrieving revision 1.222
diff -u -p -r1.222 locore.S
--- sys/arch/mips/mips/locore.S	8 Jan 2020 20:59:19 -0000	1.222
+++ sys/arch/mips/mips/locore.S	17 Jul 2020 09:25:33 -0000
@@ -348,6 +348,7 @@ NESTED(cpu_switchto, CALLFRAME_SIZ, ra)
 END(cpu_switchto)
 
 #ifdef __HAVE_FAST_SOFTINTS
+not now;
 /*
  * void softint_fast_dispatch(struct lwp *l, int s);
  *
Index: sys/arch/mips/mips/locore_mips1.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/locore_mips1.S,v
retrieving revision 1.93
diff -u -p -r1.93 locore_mips1.S
--- sys/arch/mips/mips/locore_mips1.S	8 Jun 2017 05:46:57 -0000	1.93
+++ sys/arch/mips/mips/locore_mips1.S	17 Jul 2020 09:25:33 -0000
@@ -503,6 +503,7 @@ NESTED_NOPROFILE(MIPSX(kern_intr), KERNF
 	 * high-priority interrupts to be delivered once a
 	 * low-priority interrupt handler lowers spl to execute.
 	 */
+	/* XXXNH - mipsX_subr.S leaves it alone */
 	mfc0	v1, MIPS_COP_0_STATUS
 	nop
 	or	v0, v1, MIPS_SR_INT_IE
@@ -550,9 +551,15 @@ NESTED_NOPROFILE(MIPSX(kern_intr), KERNF
 	beqz	v0, 4f				#   nope
 	 nop
 	xor	t0, v0				# clear preempt bit
+
 	INT_S	t0, CPU_INFO_SOFTINTS(s2)	# and save it.
+
+	jal	_C_LABEL(splx_noprof)		# drop to IPL_SCHED
+	 li	a0, IPL_SCHED
+
 	jal	_C_LABEL(kpreempt)		# kpreempt(pc)
-	 PTR_L	a0, TF_BASE+TF_REG_EPC(sp)
+	 li	a0, -2
+
 #endif /* __HAVE_PREEMPTION */
 4:
 #endif /* __HAVE_FAST_SOFTINTS */
@@ -667,8 +674,12 @@ NESTED_NOPROFILE(MIPSX(user_gen_exceptio
 #endif
 	move	sp, k0				# switch to kernel SP
 	move	MIPS_CURLWP, k1
-#ifndef NOFPU
-	lui	t0, %hi(MIPS_SR_COP_1_BIT)
+#ifdef NOFPU
+	li	t0, MIPS_SR_INT_IE		# reenable intrs
+	or	t0, a0
+#else
+	lui	t0, %hi(~MIPS_SR_COP_1_BIT)
+	addiu	t0, %lo(~MIPS_SR_COP_1_BIT)
 	and	t0, a0
 	beqz	t0, 1f
 	 xor	t0, a0				# turn off the FPU
@@ -676,6 +687,9 @@ NESTED_NOPROFILE(MIPSX(user_gen_exceptio
 	 nop
 1:
 #endif
+	mtc0	t0, MIPS_COP_0_STATUS
+	nop
+
 /*
  * Call the trap handler.
  */
@@ -785,14 +799,16 @@ NESTED_NOPROFILE(MIPSX(user_intr), CALLF
 	 * Also switch off the FPU.
 	 */
 	mfc0	v1, MIPS_COP_0_STATUS
-#ifndef NOFPU
-	lui	v0, %hi(MIPS_SR_COP_1_BIT)
+#ifdef NOFPU
+	li	v0, MIPS_SR_INT_IE		# reenable intrs
+	or	v0, v1
+#else
+	lui	v0, %hi(~MIPS_SR_COP_1_BIT)
+	addiu	v0, %lo(~MIPS_SR_COP_1_BIT)
 	and	v0, v1
 	or	v0, MIPS_SR_INT_IE		# make sure intrs are still on
-#else
-	li	v0, MIPS_SR_INT_IE		# reenable intrs
 #endif
-	xor	v0, v1
+
 	mtc0	v0, MIPS_COP_0_STATUS
 	nop
 
@@ -877,11 +893,14 @@ NESTED_NOPROFILE(MIPSX(user_intr), CALLF
 	REG_S	s7, CALLFRAME_SIZ+TF_REG_S7(sp)	# $23
 	REG_S	s8, CALLFRAME_SIZ+TF_REG_S8(sp)	# $30
 
-	mfc0	t0, MIPS_COP_0_STATUS
-	PTR_LA	ra, MIPSX(user_return)		# load delay
+	mfc0	t0, MIPS_COP_0_STATUS		#
+	nop
 	or	t0, MIPS_SR_INT_IE		# enable interrupts
+	mtc0	t0, MIPS_COP_0_STATUS		# enable interrupts (spl0)
+	nop
+	PTR_LA	ra, MIPSX(user_return)
 	j	_C_LABEL(ast)			# ast()
-	 mtc0	t0, MIPS_COP_0_STATUS		# enable interrupts (spl0)
+	 nop
 	.set	at
 END(MIPSX(user_intr))
 
@@ -958,13 +977,14 @@ NESTED_NOPROFILE(MIPSX(systemcall), CALL
 	 * Turn off FPU
 	 */
 #ifdef NOFPU
-	li	t0, MIPS_SR_INT_IE
+	li	t0, MIPS_SR_INT_IE		# reenable intrs
+	or	t0, a1
 #else
-	lui	t0, %hi(MIPS_SR_COP_1_BIT)
+	lui	t0, %hi(~MIPS_SR_COP_1_BIT)
+	addiu	t0, %lo(~MIPS_SR_COP_1_BIT)
 	and	t0, a1
 	ori	t0, MIPS_SR_INT_IE		# turn on IEc, enable intr.
 #endif
-	xor	t0, a1				# turns off the FPU & ints on
 	mtc0	t0, MIPS_COP_0_STATUS		# re-enable interrupts
 /*
  * Call the system call handler.
Index: sys/arch/mips/mips/mipsX_subr.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mipsX_subr.S,v
retrieving revision 1.108
diff -u -p -r1.108 mipsX_subr.S
--- sys/arch/mips/mips/mipsX_subr.S	13 Jun 2020 12:53:42 -0000	1.108
+++ sys/arch/mips/mips/mipsX_subr.S	17 Jul 2020 09:25:33 -0000
@@ -1194,6 +1194,7 @@ NESTED_NOPROFILE(MIPSX(kern_intr), KERNF
 #endif /* PARANOIA */
 
 #ifdef __HAVE_FAST_SOFTINTS
+not now;
 	and	a0, s1, MIPS_SOFT_INT_MASK	# were softints enabled?
 	beqz	a0, 4f				#   nope
 	 nop
@@ -1224,6 +1225,25 @@ NESTED_NOPROFILE(MIPSX(kern_intr), KERNF
 	 li	a0, -2
 #endif /* __HAVE_PREEMPTION */
 4:
+#else
+
+	bnez	t1, 5f
+
+	/*
+	 * Check pending asynchronous traps.
+	 */
+	INT_L	v0, L_MD_ASTPENDING(MIPS_CURLWP)# any pending ast?
+	beqz	v0, 5f
+	 nop
+
+	/*
+	 * We have pending asynchronous traps; all the state is already saved.
+	 */
+	jal	_C_LABEL(ast)
+	 nop
+
+5:
+
 #endif /* __HAVE_FAST_SOFTINTS */
 	/*
 	 * Interrupts handled, restore registers and return from the interrupt.
@@ -1234,6 +1254,7 @@ NESTED_NOPROFILE(MIPSX(kern_intr), KERNF
 #else
 	mfc0	v0, MIPS_COP_0_STATUS		# read it
 	MFC0_HAZARD
+#	XXX - does this always dsiable???
 	xor	v0, MIPS_SR_INT_IE		# disable interrupts
 	mtc0	v0, MIPS_COP_0_STATUS		# write it
 #endif
@@ -2723,7 +2744,12 @@ LEAF_NOPROFILE(MIPSX(cpu_switch_resume))
 	INT_ADD a2, a1, MIPS3_PG_NEXT		# a2 = upper half
 #endif
 #else
+#if (USPACE > PAGE_SIZE)
 	INT_L	a2, L_MD_UPTE_1(a0)		# a2 = upte[1]
+#else
+#error incomplete
+	li	a2, MIPS3_PG_G			# a2 = invalid/global
+#endif
 #endif /* (PGSHIFT & 1) */
 	PTR_L	v0, L_PCB(a0)			# va = l->l_addr
 #if VM_MIN_KERNEL_ADDRESS == MIPS_KSEG2_START
@@ -3103,3 +3129,21 @@ MIPSX(excpt_sw):
 loongson2_xtlb_miss_str:
 	.string "loongson2_xtlb_miss"
 #endif
+
+
+
+#if 0
+	if (loongson2_xtlb_miss - loongson2_tlb_miss != 0x80)
+		panic("startup: %s vector code not 128 bytes in length",
+		    "UTLB");
+	if (loongson2_cache - loongson2_xtlb_miss != 0x80)
+		panic("startup: %s vector code not 128 bytes in length",
+		    "XTLB");
+	if (loongson2_exception - loongson2_cache != 0x80)
+		panic("startup: %s vector code not 128 bytes in length",
+		    "Cache error");
+	if (loongson2_exception_end - loongson2_exception > 0x80)
+		panic("startup: %s vector code too large",
+		    "General exception");
+
+#endif
Index: sys/arch/mips/mips/mips_fixup.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mips_fixup.c,v
retrieving revision 1.20
diff -u -p -r1.20 mips_fixup.c
--- sys/arch/mips/mips/mips_fixup.c	6 Apr 2019 03:06:26 -0000	1.20
+++ sys/arch/mips/mips/mips_fixup.c	17 Jul 2020 09:25:34 -0000
@@ -56,6 +56,7 @@ mips_fixup_exceptions(mips_fixup_callbac
 	} else {
 		start = (uint32_t *)(intptr_t)(ebase & ~MIPS_EBASE_CPUNUM);
 	}
+printf("%s: ebase %x mips_cpu_id %x start %p\n", __func__, ebase, mips_options.mips_cpu_id, start);
 #else
 	uint32_t * const start = (uint32_t *)MIPS_KSEG0_START;
 #endif
@@ -246,17 +247,16 @@ fixup_mips_jump(uint32_t *insnp, const s
 
 	KASSERT((insn << 6) == (jfi->jfi_real << 6));
 
-#ifdef DEBUG
-#if 0
+#ifdef DEBUG_VERBOSE
 	int32_t va = ((intptr_t) insnp >> 26) << 26;
+	uint32_t opcode = insn >> 26;
 	printf("%s: %08x: [%08x] %s %08x -> [%08x] %s %08x\n",
 	    __func__, (int32_t)(intptr_t)insnp,
 	    insn, opcode == OPCODE_J ? "j" : "jal",
-	    va | (jfi->jfo_stub << 2),
+	    va | (jfi->jfi_stub << 2),
 	    *insnp, opcode == OPCODE_J ? "j" : "jal",
 	    va | (jfi->jfi_real << 2));
 #endif
-#endif
 	*insnp = insn;
 }
 
Index: sys/arch/mips/mips/mips_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mips_machdep.c,v
retrieving revision 1.295
diff -u -p -r1.295 mips_machdep.c
--- sys/arch/mips/mips/mips_machdep.c	13 Jul 2020 05:20:45 -0000	1.295
+++ sys/arch/mips/mips/mips_machdep.c	17 Jul 2020 09:25:34 -0000
@@ -1399,9 +1399,11 @@ mips_vector_init(const struct splsw *spl
 	 * Now that the splsw and locoresw have been filled in, fixup the
 	 * jumps to any stubs to actually jump to the real routines.
 	 */
+#if 0
 	extern uint32_t _ftext[];
 	extern uint32_t _etext[];
 	mips_fixup_stubs(_ftext, _etext);
+#endif
 
 #if (MIPS3 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
 	/*
Index: sys/arch/mips/mips/mips_softint.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mips_softint.c,v
retrieving revision 1.8
diff -u -p -r1.8 mips_softint.c
--- sys/arch/mips/mips/mips_softint.c	8 Jan 2020 17:38:42 -0000	1.8
+++ sys/arch/mips/mips/mips_softint.c	17 Jul 2020 09:25:34 -0000
@@ -89,6 +89,7 @@ softint_trigger(uintptr_t si)
 #define	SOFTINT_MASK_1	(SOFTINT_SERIAL_MASK | SOFTINT_NET_MASK)
 #define	SOFTINT_MASK_0	(SOFTINT_CLOCK_MASK  | SOFTINT_BIO_MASK)
 
+/* XXX ci_softints atomic op ??? */
 /*
  * Helper macro.
  *
@@ -108,7 +109,7 @@ void
 softint_process(uint32_t ipending)
 {
 	struct cpu_info * const ci = curcpu();
-	u_int mask;
+	u_int mask = 0;
 
 	KASSERT((ipending & MIPS_SOFT_INT_MASK) != 0);
 	KASSERT((ipending & ~MIPS_SOFT_INT_MASK) == 0);
@@ -118,17 +119,15 @@ softint_process(uint32_t ipending)
 	    "%s: cpu%u (%p): ci_mtx_count (%d) != 0",
 	     __func__, cpu_index(ci), ci, ci->ci_mtx_count);
 
+	/*
+	 * Since we run at splhigh, 
+	 */
 	if (ipending & MIPS_SOFT_INT_MASK_0) {
-		/*
-		 * Since we run at splhigh, 
-		 */
-		mask = SOFTINT_MASK_1 | SOFTINT_MASK_0;
-		ipending |= MIPS_SOFT_INT_MASK_1;
-	} else {
-		KASSERT(ipending & MIPS_SOFT_INT_MASK_1);
-		mask = SOFTINT_MASK_1;
+		mask |= SOFTINT_MASK_0;
+	}
+	if (ipending & MIPS_SOFT_INT_MASK_1) {
+		mask |= SOFTINT_MASK_1;
 	}
-
 	for (;;) {
 		u_int softints = ci->ci_softints & mask;
 		if (softints == 0)
Index: sys/arch/mips/mips/spl.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/spl.S,v
retrieving revision 1.17
diff -u -p -r1.17 spl.S
--- sys/arch/mips/mips/spl.S	12 Apr 2019 21:12:21 -0000	1.17
+++ sys/arch/mips/mips/spl.S	17 Jul 2020 09:25:34 -0000
@@ -80,6 +80,10 @@ _splraise:
 	or	v1, MIPS_INT_MASK		# enable all interrupts
 	xor	a0, v1				# disable ipl's masked bits
 	DYNAMIC_STATUS_MASK(a0,v0)		# machine dependent masking
+
+#if defined(MIPSNNR2)
+	di
+#else
 #if !defined(__mips_o32)
 	or	v1, MIPS_SR_INT_IE		#
 	xor	v1, MIPS_SR_INT_IE		# clear interrupt enable bit
@@ -87,7 +91,9 @@ _splraise:
 #else
 	mtc0	zero, MIPS_COP_0_STATUS		## disable interrupts
 #endif
+#endif
 	COP0_SYNC
+
 #ifdef MULTIPROCESSOR
 	PTR_L	a3, L_CPU(MIPS_CURLWP)		## make sure curcpu is correct
 	NOP_L					## load delay
@@ -137,6 +143,10 @@ STATIC_XLEAF(_splsw_splx_noprof)		# does
 	xor	a1, MIPS_INT_MASK		# invert SR bits
 	or	v1, a1				# set any bits for this IPL
 	DYNAMIC_STATUS_MASK(v1,t0)		# machine dependent masking
+
+#if defined(MIPSNNR2)
+	di
+#else
 #if !defined(__mips_o32)
 	or	v0, v1, MIPS_SR_INT_IE		#
 	xor	v0, MIPS_SR_INT_IE		# clear interrupt enable bit
@@ -144,7 +154,9 @@ STATIC_XLEAF(_splsw_splx_noprof)		# does
 #else
 	mtc0	zero, MIPS_COP_0_STATUS		## disable interrupts
 #endif
+#endif
 	COP0_SYNC
+
 	INT_S	a0, CPU_INFO_CPL(a3)		## save IPL in cpu_info (KSEG0)
 	mtc0	v1, MIPS_COP_0_STATUS		## store back
 	COP0_SYNC
@@ -178,6 +190,10 @@ STATIC_LEAF(_splsw_spl0)
 	MFC0_HAZARD				# load delay
 	or	v0, a0, v1
 	DYNAMIC_STATUS_MASK(v0,t0)		# machine dependent masking
+
+#if defined(MIPSNNR2)
+	di
+#else
 #if !defined(__mips_o32)
 	or	v1, v0, MIPS_SR_INT_IE		#
 	xor	v1, MIPS_SR_INT_IE		# clear interrupt enable bit
@@ -185,6 +201,7 @@ STATIC_LEAF(_splsw_spl0)
 #else
 	mtc0	zero, MIPS_COP_0_STATUS		## disable interrupts
 #endif
+#endif
 	COP0_SYNC
 #if IPL_NONE == 0
 	INT_S	zero, CPU_INFO_CPL(a3)		## set ipl to 0
@@ -196,8 +213,11 @@ STATIC_LEAF(_splsw_spl0)
 END(_splsw_spl0)
 
 STATIC_LEAF(_splsw_setsoftintr)
-	mfc0	v1, MIPS_COP_0_STATUS		# save status register
+#if defined(MIPSNNR2)
+	di
+#else
 #if !defined(__mips_o32)
+	mfc0	v1, MIPS_COP_0_STATUS		# save status register
 	MFC0_HAZARD				# load delay
 	or	v0, v1, MIPS_SR_INT_IE		#
 	xor	v0, MIPS_SR_INT_IE		# clear interrupt enable bit
@@ -205,17 +225,25 @@ STATIC_LEAF(_splsw_setsoftintr)
 #else
 	mtc0	zero, MIPS_COP_0_STATUS		## disable interrupts
 #endif
+#endif
 	COP0_SYNC
 	mfc0	v0, MIPS_COP_0_CAUSE		# fetch cause register
 	MFC0_HAZARD				# load delay
 	or	v0, v0, a0			# set soft intr. bits
 	mtc0	v0, MIPS_COP_0_CAUSE		# store back
 	COP0_SYNC
+#if defined(MIPSNNR2)
+	ei
+#else
 	mtc0	v1, MIPS_COP_0_STATUS		# enable interrupts
+#endif
 	JR_HB_RA				# return (clear hazards)
 END(_splsw_setsoftintr)
 
 STATIC_LEAF(_splsw_clrsoftintr)
+#if defined(MIPSNNR2)
+	di
+#else
 	mfc0	v1, MIPS_COP_0_STATUS		# save status register
 #if !defined(__mips_o32)
 	MFC0_HAZARD				# load delay
@@ -225,13 +253,18 @@ STATIC_LEAF(_splsw_clrsoftintr)
 #else
 	mtc0	zero, MIPS_COP_0_STATUS		## disable interrupts
 #endif
+#endif
 	COP0_SYNC
 	mfc0	v0, MIPS_COP_0_CAUSE		# fetch cause register
 	nor	a0, zero, a0			# bitwise inverse of A0
 	and	v0, v0, a0			# clear soft intr. bits
 	mtc0	v0, MIPS_COP_0_CAUSE		# store back
 	COP0_SYNC
+#if defined(MIPSNNR2)
+	ei
+#else
 	mtc0	v1, MIPS_COP_0_STATUS		# enable interrupts
+#endif
 	JR_HB_RA				# return (clear hazards)
 END(_splsw_clrsoftintr)
 
@@ -252,7 +285,7 @@ STATIC_XLEAF(_splsw_splhigh_noprof)
 	PTR_L	a3, L_CPU(MIPS_CURLWP)
 	NOP_L					# load delay
 	INT_L	v0, CPU_INFO_CPL(a3)		# get current IPL from cpu_info
-	li	a1, IPL_HIGH			# 
+	li	a1, IPL_HIGH			#
 	beq	v0, a1, 1f			# don't do anything if IPL_HIGH
 	 nop					# branch delay
 	mfc0	v1, MIPS_COP_0_STATUS		# fetch status register
Index: sys/arch/mips/mips/syscall.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/syscall.c,v
retrieving revision 1.49
diff -u -p -r1.49 syscall.c
--- sys/arch/mips/mips/syscall.c	31 Jul 2016 07:06:24 -0000	1.49
+++ sys/arch/mips/mips/syscall.c	17 Jul 2020 09:25:34 -0000
@@ -196,7 +196,7 @@ EMULNAME(syscall)(struct lwp *l, u_int s
 			 * Start copying args skipping the register slots
 			 * slots on the stack.
 			 */
-			usp = reg->r_regs[_R_SP] + nsaved*sizeof(register_t);
+			usp = reg->r_regs[_R_SP] + nsaved * sizeof(register_t);
 			error = copyin((register_t *)usp, &copyargs[nregs],
 			    (nargs - nregs) * sizeof(copyargs[0]));
 			if (error)
@@ -314,6 +314,10 @@ EMULNAME(syscall)(struct lwp *l, u_int s
 	printf("\n");
 #endif
 
+if (trace_is_enabled(l->l_proc)) {
+	cpu_Debugger();
+}
+
 	error = sy_invoke(callp, l, args, &reg->r_regs[_R_V0], code);
 
 	switch (error) {
Index: sys/arch/mips/mips/trap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/trap.c,v
retrieving revision 1.255
diff -u -p -r1.255 trap.c
--- sys/arch/mips/mips/trap.c	13 Jul 2020 09:00:40 -0000	1.255
+++ sys/arch/mips/mips/trap.c	17 Jul 2020 09:25:34 -0000
@@ -142,6 +142,7 @@ md_child_return(struct lwp *l)
 #endif
 #define KERNLAND_P(x) ((intptr_t)(x) < 0)
 
+int nhddb = 0;
 /*
  * Trap is called from locore to handle most types of processor traps.
  * System calls are broken out for efficiency.  MIPS can handle software
@@ -405,11 +406,17 @@ trap(uint32_t status, uint32_t cause, va
 		pcb->pcb_onfault = onfault;
 
 #if defined(VMFAULT_TRACE)
-		if (!KERNLAND_P(va))
+		if (!KERNLAND_P(va)) {
 			printf(
 			    "uvm_fault(%p (pmap %p), %#"PRIxVADDR
 			    " (%"PRIxVADDR"), %d) -> %d at pc %#"PRIxVADDR"\n",
 			    map, vm->vm_map.pmap, va, vaddr, ftype, rv, pc);
+			if (va == 0x7dfd6000) {
+				extern int kernhist_print_enabled;
+				kernhist_print_enabled = 1;
+			}
+		}
+
 #endif
 		/*
 		 * If this was a stack access we keep track of the maximum
@@ -641,6 +648,8 @@ trap(uint32_t status, uint32_t cause, va
 		    i+0, utf->tf_regs[i+0], i+1, utf->tf_regs[i+1],
 		    i+2, utf->tf_regs[i+2], i+3, utf->tf_regs[i+3]);
 	}
+if (nhddb == 1)
+	kdb_trap(type, &utf->tf_registers);
 #endif
 	(*p->p_emul->e_trapsignal)(l, &ksi);
 	if ((type & T_USER) == 0) {
@@ -683,14 +692,13 @@ ast(void)
 			ADDUPROF(l);
 		}
 
-		userret(l);
-
 		if (l->l_cpu->ci_want_resched) {
 			/*
 			 * We are being preempted.
 			 */
 			preempt();
 		}
+		userret(l);
 	}
 }
 
Index: sys/arch/mips/mips/vm_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/vm_machdep.c,v
retrieving revision 1.160
diff -u -p -r1.160 vm_machdep.c
--- sys/arch/mips/mips/vm_machdep.c	20 Nov 2019 19:37:52 -0000	1.160
+++ sys/arch/mips/mips/vm_machdep.c	17 Jul 2020 09:25:34 -0000
@@ -67,6 +67,23 @@ __KERNEL_RCSID(0, "$NetBSD: vm_machdep.c
 
 paddr_t kvtophys(vaddr_t);	/* XXX */
 
+
+int nhpgshift = PGSHIFT;
+int nhpgsz = PAGE_SIZE;
+int nhupages = UPAGES;
+#ifdef ENABLE_MIPS_16KB_PAGE
+int nheable16k = ENABLE_MIPS_16KB_PAGE;
+#endif
+#ifdef ENABLE_MIPS_8KB_PAGE
+int nhenable8k =  ENABLE_MIPS_8KB_PAGE;
+#endif
+#ifdef ENABLE_MIPS_4KB_PAGE
+int nhenable4k = ENABLE_MIPS_4KB_PAGE;
+#endif
+#ifdef __mips
+int nhmips = __mips;
+#endif
+
 /*
  * cpu_lwp_fork: Finish a fork operation, with lwp l2 nearly set up.
  * Copy and update the pcb and trapframe, making the child ready to run.
@@ -120,6 +137,10 @@ cpu_lwp_fork(struct lwp *l1, struct lwp 
 		l2->l_md.md_upte[i] = 0;
 	}
 	if (!pmap_md_direct_mapped_vaddr_p(ua2)) {
+		/*
+		 * UPAGES has to be 2 for 4KB PAGE_SIZE
+		 * UPAGES has to be 1 for >= 8KB PAGE_SIZE
+		 */
 		CTASSERT((PGSHIFT == 12) == (UPAGES == 2));
 		pt_entry_t * const pte = pmap_pte_lookup(pmap_kernel(), ua2);
 		const uint32_t x = MIPS_HAS_R4K_MMU
Index: sys/kern/kern_history.c
===================================================================
RCS file: /cvsroot/src/sys/kern/kern_history.c,v
retrieving revision 1.19
diff -u -p -r1.19 kern_history.c
--- sys/kern/kern_history.c	9 Oct 2019 05:59:51 -0000	1.19
+++ sys/kern/kern_history.c	17 Jul 2020 09:25:41 -0000
@@ -226,6 +226,14 @@ kernhist_dumpmask(uint32_t bitmask)	/* X
 
 	if ((bitmask & KERNHIST_UVMLOANHIST) || bitmask == 0)
 		hists[i++] = &loanhist;
+
+#if 0
+	if ((bitmask & KERNHIST_PMAPHIST) || bitmask == 0)
+		hists[i++] = &pmaphist;
+
+	if ((bitmask & KERNHIST_PMAPEXECHIST) || bitmask == 0)
+		hists[i++] = &pmapexechist;
+#endif
 #endif
 
 #ifdef USB_DEBUG
@@ -270,6 +278,10 @@ kernhist_print(void *addr, size_t count,
 		hists[i++] = &pdhist;
 		hists[i++] = &ubchist;
 		hists[i++] = &loanhist;
+#if 0
+		hists[i++] = &pmaphist;
+		hists[i++] = &pmapexechist;
+#endif
 #endif
 #ifdef USB_DEBUG
 		hists[i++] = &usbhist;
Index: sys/kern/kern_synch.c
===================================================================
RCS file: /cvsroot/src/sys/kern/kern_synch.c,v
retrieving revision 1.349
diff -u -p -r1.349 kern_synch.c
--- sys/kern/kern_synch.c	23 May 2020 23:42:43 -0000	1.349
+++ sys/kern/kern_synch.c	17 Jul 2020 09:25:41 -0000
@@ -94,6 +94,7 @@ __KERNEL_RCSID(0, "$NetBSD: kern_synch.c
 #include <sys/atomic.h>
 #include <sys/syslog.h>
 
+#include <uvm/uvm.h>
 #include <uvm/uvm_extern.h>
 
 #include <dev/lockstat.h>
@@ -518,7 +519,7 @@ nextlwp(struct cpu_info *ci, struct sche
 	/*
 	 * Let sched_nextlwp() select the LWP to run the CPU next.
 	 * If no LWP is runnable, select the idle LWP.
-	 * 
+	 *
 	 * On arrival here LWPs on a run queue are locked by spc_mutex which
 	 * is currently held.  Idle LWPs are always locked by spc_lwplock,
 	 * which may or may not be held here.  On exit from this code block,
@@ -583,6 +584,9 @@ mi_switch(lwp_t *l)
 	KASSERT(mutex_owned(curcpu()->ci_schedstate.spc_mutex));
 	KASSERTMSG(l->l_blcnt == 0, "kernel_lock leaked");
 
+	UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
+	UVMHIST_LOG(maphist, "l %p l_cpu %p curlwp %p curcpu %p", l, l->l_cpu, curlwp, curcpu());
+
 	kstack_check_magic(l);
 
 	binuptime(&bt);
@@ -760,6 +764,9 @@ mi_switch(lwp_t *l)
 			(*dtrace_vtime_switch_func)(newl);
 		}
 
+UVMHIST_LOG(maphist, "oldlwp %p newlwp %p returning %d newlwp->l_cpu %p", l, newl, returning, newl->l_cpu);
+
+
 		/*
 		 * We must ensure not to come here from inside a read section.
 		 */
@@ -918,7 +925,7 @@ setrunnable(struct lwp *l)
 /*
  * suspendsched:
  *
- *	Convert all non-LW_SYSTEM LSSLEEP or LSRUN LWPs to LSSUSPENDED. 
+ *	Convert all non-LW_SYSTEM LSSLEEP or LSRUN LWPs to LSSUSPENDED.
  */
 void
 suspendsched(void)
@@ -977,8 +984,8 @@ suspendsched(void)
 	mutex_exit(&proc_lock);
 
 	/*
-	 * Kick all CPUs to make them preempt any LWPs running in user mode. 
-	 * They'll trap into the kernel and suspend themselves in userret(). 
+	 * Kick all CPUs to make them preempt any LWPs running in user mode.
+	 * They'll trap into the kernel and suspend themselves in userret().
 	 *
 	 * Unusually, we don't hold any other scheduler object locked, which
 	 * would keep preemption off for sched_resched_cpu(), so disable it
Index: sys/sys/kernhist.h
===================================================================
RCS file: /cvsroot/src/sys/sys/kernhist.h,v
retrieving revision 1.25
diff -u -p -r1.25 kernhist.h
--- sys/sys/kernhist.h	14 Aug 2018 11:39:10 -0000	1.25
+++ sys/sys/kernhist.h	17 Jul 2020 09:25:46 -0000
@@ -121,6 +121,8 @@ LIST_HEAD(kern_history_head, kern_histor
 #define	KERNHIST_USBHIST	0x00000010	/* usbhist */
 #define	KERNHIST_SCDEBUGHIST	0x00000020	/* scdebughist */
 #define	KERNHIST_BIOHIST	0x00000040	/* biohist */
+#define KERNHIST_PMAPHIST	0x00000080	/* pmaphist */
+#define KERNHIST_PMAPEXECHIST	0x00000100	/* pmapexechist */
 
 #ifdef _KERNEL
 
Index: sys/sys/userret.h
===================================================================
RCS file: /cvsroot/src/sys/sys/userret.h,v
retrieving revision 1.33
diff -u -p -r1.33 userret.h
--- sys/sys/userret.h	26 Mar 2020 20:19:06 -0000	1.33
+++ sys/sys/userret.h	17 Jul 2020 09:25:46 -0000
@@ -114,7 +114,9 @@ mi_userret(struct lwp *l)
 	KPREEMPT_ENABLE(l);
 
 	LOCKDEBUG_BARRIER(NULL, 0);
+#ifdef __HAVE_PREEMPTION
 	KASSERT(l->l_nopreempt == 0);
+#endif
 	PSREF_DEBUG_BARRIER();
 	KASSERT(l->l_psrefs == 0);
 }
Index: sys/uvm/pmap/pmap_tlb.c
===================================================================
RCS file: /cvsroot/src/sys/uvm/pmap/pmap_tlb.c,v
retrieving revision 1.33
diff -u -p -r1.33 pmap_tlb.c
--- sys/uvm/pmap/pmap_tlb.c	14 Apr 2020 05:43:57 -0000	1.33
+++ sys/uvm/pmap/pmap_tlb.c	17 Jul 2020 09:25:46 -0000
@@ -218,6 +218,7 @@ pmap_tlb_pai_check(struct pmap_tlb_info 
 	struct pmap_asid_info *pai;
 	if (!locked_p)
 		TLBINFO_LOCK(ti);
+	KASSERT(TLBINFO_OWNED(ti));
 	LIST_FOREACH(pai, &ti->ti_pais, pai_link) {
 		KASSERT(pai != NULL);
 		KASSERT(PAI_PMAP(pai, ti) != pmap_kernel());
@@ -543,9 +544,8 @@ pmap_tlb_shootdown_process(void)
 #endif
 
 	KASSERT(cpu_intr_p());
-	KASSERTMSG(ci->ci_cpl >= IPL_SCHED,
-	    "%s: cpl (%d) < IPL_SCHED (%d)",
-	    __func__, ci->ci_cpl, IPL_SCHED);
+	KASSERTMSG(ci->ci_cpl >= IPL_SCHED, "%s: ci %p cpl (%d) < IPL_SCHED (%d)",
+	    __func__, ci, ci->ci_cpl, IPL_SCHED);
 
 	TLBINFO_LOCK(ti);
 
@@ -664,8 +664,8 @@ pmap_tlb_shootdown_bystanders(pmap_t pm)
 		if (!kcpuset_intersecting_p(pm_active, ti->ti_kcpuset))
 			continue;
 		struct pmap_asid_info * const pai = PMAP_PAI(pm, ti);
-		kcpuset_remove(pm_active, ti->ti_kcpuset);
 		TLBINFO_LOCK(ti);
+		kcpuset_remove(pm_active, ti->ti_kcpuset);
 		cpuid_t j = kcpuset_ffs_intersecting(pm->pm_onproc,
 		    ti->ti_kcpuset);
 		// post decrement since ffs returns bit + 1 or 0 if no bit
@@ -756,6 +756,9 @@ pmap_tlb_update_addr(pmap_t pm, vaddr_t 
 		KASSERTMSG((flags & PMAP_TLB_INSERT) == 0 || rv == 1,
 		    "pmap %p (asid %u) va %#"PRIxVADDR" pte %#"PRIxPTE" rv %d",
 		    pm, pai->pai_asid, va, pte_value(pte), rv);
+#if defined(DEBUG) && !defined(MULTIPROCESSOR) && 0
+	        pmap_tlb_check(pm, pmap_md_tlb_check_entry);
+#endif /* DEBUG */
 	}
 #if defined(MULTIPROCESSOR) && defined(PMAP_TLB_NEED_SHOOTDOWN)
 	if (flags & PMAP_TLB_NEED_IPI)
@@ -788,6 +791,9 @@ pmap_tlb_invalidate_addr(pmap_t pm, vadd
 		    va, pai->pai_asid, 0, 0);
 		tlb_invalidate_addr(va, pai->pai_asid);
 		pmap_tlb_asid_check();
+#if defined(DEBUG) && !defined(MULTIPROCESSOR) && 0
+	        pmap_tlb_check(pm, pmap_md_tlb_check_entry);
+#endif /* DEBUG */
 	}
 #if defined(MULTIPROCESSOR) && defined(PMAP_TLB_NEED_SHOOTDOWN)
 	pm->pm_shootdown_pending = 1;
@@ -995,9 +1001,11 @@ pmap_tlb_asid_deactivate(pmap_t pm)
 	UVMHIST_LOG(maphist, " <-- done (pm=%#jx)", (uintptr_t)pm, 0, 0, 0);
 	tlb_set_asid(KERNEL_PID);
 	pmap_tlb_pai_check(cpu_tlb_info(curcpu()), false);
+#if 0
 #if defined(DEBUG)
 	pmap_tlb_asid_check();
 #endif
+#endif
 }
 
 void
Index: sys/uvm/pmap/pmap_tlb.h
===================================================================
RCS file: /cvsroot/src/sys/uvm/pmap/pmap_tlb.h,v
retrieving revision 1.13
diff -u -p -r1.13 pmap_tlb.h
--- sys/uvm/pmap/pmap_tlb.h	19 Feb 2018 22:01:15 -0000	1.13
+++ sys/uvm/pmap/pmap_tlb.h	17 Jul 2020 09:25:46 -0000
@@ -96,6 +96,7 @@ struct pmap_asid_info {
 
 #define	TLBINFO_LOCK(ti)		mutex_spin_enter((ti)->ti_lock)
 #define	TLBINFO_UNLOCK(ti)		mutex_spin_exit((ti)->ti_lock)
+#define	TLBINFO_OWNED(ti)		mutex_owned((ti)->ti_lock)
 #define	PMAP_PAI_ASIDVALID_P(pai, ti)	((pai)->pai_asid != 0)
 #define	PMAP_PAI(pmap, ti)		(&(pmap)->pm_pai[tlbinfo_index(ti)])
 #define	PAI_PMAP(pai, ti)	\