? sys/cscope.out
? sys/arch/cobalt/conf/NOCACHE
? sys/arch/evbmips/conf/ERLITE.MP
? sys/arch/mips/mips/ktrace.out
? sys/arch/mips/mips/mipsX_subr.S.new
? sys/arch/mips/mips/mipsnnr2_spl.S
? sys/arch/mips/mips/splX_subr.S
Index: sys/arch/cobalt/conf/GENERIC
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/conf/GENERIC,v
retrieving revision 1.166
diff -u -p -w -b -r1.166 GENERIC
--- sys/arch/cobalt/conf/GENERIC	25 Jan 2020 18:38:35 -0000	1.166
+++ sys/arch/cobalt/conf/GENERIC	8 Mar 2020 20:36:15 -0000
@@ -45,6 +45,8 @@ options 	BUFQ_PRIOCSCAN
 options 	DIAGNOSTIC	# extra kernel sanity checking
 options 	DEBUG		# extra kernel debugging support
 options 	DDB		# kernel dynamic debugger
+options 	UVMHIST
+options 	UVMHIST_MAPHIST_SIZE=10000
 #options 	DDB_HISTORY_SIZE=100 # enable history editing in DDB
 makeoptions	DEBUG="-g"	# compile full symbol table
 makeoptions	CPUFLAGS="-march=vr5000"
Index: sys/arch/evbmips/conf/CI20
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/conf/CI20,v
retrieving revision 1.29
diff -u -p -w -b -r1.29 CI20
--- sys/arch/evbmips/conf/CI20	19 Jan 2020 01:25:05 -0000	1.29
+++ sys/arch/evbmips/conf/CI20	8 Mar 2020 20:36:15 -0000
@@ -32,7 +32,12 @@ options 	CONSPEED=115200	# u-boot defaul
 # Size reduction options
 #options 	VNODE_OP_NOINLINE
 #options 	PIPE_SOCKETPAIR
-options		SOSEND_NO_LOAN
+#options		SOSEND_NO_LOAN
+
+
+#options 	UVMHIST
+#options		UVMHIST_PRINT
+#options		KERNHIST_DELAY=0
 
 # Standard system options
 options 	KTRACE		# system call tracing support
@@ -43,7 +48,8 @@ options 	NTP		# network time protocol
 
 # Debugging options
 options 	DIAGNOSTIC	# extra kernel sanity checking
-#options 	DEBUG		# extra kernel debugging support
+options 	DEBUG		# extra kernel debugging support
+options 	DEBUG_VERBOSE	# extra kernel debugging support
 #options 	USERCONF	# userconf(4) support
 #options 	SYSCTL_INCLUDE_DESCR	# Include sysctl descriptions in kernel
 options 	DDB		# kernel dynamic debugger
Index: sys/arch/evbmips/conf/ERLITE
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/conf/ERLITE,v
retrieving revision 1.24
diff -u -p -w -b -r1.24 ERLITE
--- sys/arch/evbmips/conf/ERLITE	19 Jan 2020 01:25:05 -0000	1.24
+++ sys/arch/evbmips/conf/ERLITE	8 Mar 2020 20:36:15 -0000
@@ -24,7 +24,10 @@ maxusers	32
 # Size reduction options
 #options 	VNODE_OP_NOINLINE
 #options 	PIPE_SOCKETPAIR
-#options 	SOSEND_NO_LOAN
+
+
+options 	UVMHIST
+options 	UVMHIST_MAPHIST_SIZE=10000
 
 # Standard system options
 options 	KTRACE		# system call tracing support
Index: sys/arch/evbmips/conf/std.ingenic
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/conf/std.ingenic,v
retrieving revision 1.2
diff -u -p -w -b -r1.2 std.ingenic
--- sys/arch/evbmips/conf/std.ingenic	11 Jul 2015 19:01:17 -0000	1.2
+++ sys/arch/evbmips/conf/std.ingenic	8 Mar 2020 20:36:15 -0000
@@ -6,7 +6,9 @@ include		"conf/std"	# MI standard option
 options		EXEC_ELF32	# exec ELF32 binaries
 options		EXEC_SCRIPT	# exec #! scripts
 
+options 	MIPS32R2
 makeoptions	CPUFLAGS+="-mips32r2"
+
 makeoptions	DEFTEXTADDR="0x80020000"
 makeoptions	BOARDTYPE="ingenic"
 
Index: sys/arch/evbmips/include/types.h
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/include/types.h,v
retrieving revision 1.10
diff -u -p -w -b -r1.10 types.h
--- sys/arch/evbmips/include/types.h	26 Jan 2017 15:55:09 -0000	1.10
+++ sys/arch/evbmips/include/types.h	8 Mar 2020 20:36:15 -0000
@@ -3,7 +3,9 @@
 #ifndef _EVBMIPS_TYPES_H_
 #define	_EVBMIPS_TYPES_H_
 
+#if 0
 #define	_MIPS_PADDR_T_64BIT
+#endif
 
 #include <mips/types.h>
 
Index: sys/arch/evbmips/ingenic/clock.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/ingenic/clock.c,v
retrieving revision 1.10
diff -u -p -w -b -r1.10 clock.c
--- sys/arch/evbmips/ingenic/clock.c	21 May 2017 06:49:12 -0000	1.10
+++ sys/arch/evbmips/ingenic/clock.c	8 Mar 2020 20:36:15 -0000
@@ -113,6 +113,7 @@ cpu_initclocks(void)
 #endif
 	writereg(JZ_ICMCR0, 0x0c000000); /* TCU2, OST */
 	spl0();
+
 #ifdef INGENIC_CLOCK_DEBUG
 	printf("TFR: %08x\n", readreg(JZ_TC_TFR));
 	printf("TMR: %08x\n", readreg(JZ_TC_TMR));
@@ -194,7 +195,6 @@ int cnt = 99;
 void
 ingenic_clockintr(struct clockframe *cf)
 {
-	int s = splsched();
 	struct cpu_info * const ci = curcpu();
 #ifdef USE_OST
 	uint32_t new_cnt;
@@ -240,5 +240,4 @@ ingenic_clockintr(struct clockframe *cf)
 	mips_cp0_corembox_write(1, 1 << IPI_CLOCK);
 #endif
 	hardclock(cf);
-	splx(s);
 }
Index: sys/arch/evbmips/ingenic/cpu.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/ingenic/cpu.c,v
retrieving revision 1.4
diff -u -p -w -b -r1.4 cpu.c
--- sys/arch/evbmips/ingenic/cpu.c	21 May 2017 06:49:12 -0000	1.4
+++ sys/arch/evbmips/ingenic/cpu.c	8 Mar 2020 20:36:15 -0000
@@ -75,8 +75,9 @@ cpu_attach(device_t parent, device_t sel
 {
 	struct cpu_info *ci = curcpu();
 	int unit;
-
+	aprint_normal(": inctl %#x", mipsNN_cp0_intctl_read());
 	if ((unit = device_unit(self)) > 0) {
+
 #ifdef MULTIPROCESSOR
 		uint32_t vec, reg;
 		int bail = 10000;
@@ -85,6 +86,7 @@ cpu_attach(device_t parent, device_t sel
 		startup_cpu_info->ci_cpu_freq = ci->ci_cpu_freq;
 		ci = startup_cpu_info;
 		wbflush();
+
 		vec = (uint32_t)&ingenic_wakeup;
 		reg = mips_cp0_corereim_read();
 		reg &= ~REIM_ENTRY_M;
@@ -120,6 +122,12 @@ cpu_attach(device_t parent, device_t sel
 	    (ci->ci_cpu_freq % 1000000) / 10000,
 	    ci->ci_cycles_per_hz, ci->ci_divisor_delay);
 
+	aprint_normal_dev(self, ": inctl %08x ebase %08xx\n", mipsNN_cp0_intctl_read(), mipsNN_cp0_ebase_read());
+	aprint_normal_dev(self, ": cnfg0 %08x cnfg1 %#08x\n", mips3_cp0_config_read(), mipsNN_cp0_config1_read());
+	aprint_normal_dev(self, ": cnfg2 %08x cnfg3 %#08x\n", mipsNN_cp0_config2_read(), mipsNN_cp0_config3_read());
+	aprint_normal_dev(self, ": cnfg4 %08x cnfg5 %#08x\n", mipsNN_cp0_config4_read(), mipsNN_cp0_config5_read());
+	aprint_normal_dev(self, ": cnfg6 %08x cnfg7 %#08x\n", mipsNN_cp0_config6_read(), mipsNN_cp0_config7_read());
+
 	aprint_normal_dev(self, "");
 	cpu_identify(self);
 	cpu_attach_common(self, ci);
Index: sys/arch/evbmips/ingenic/intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/ingenic/intr.c,v
retrieving revision 1.13
diff -u -p -w -b -r1.13 intr.c
--- sys/arch/evbmips/ingenic/intr.c	21 May 2017 06:49:12 -0000	1.13
+++ sys/arch/evbmips/ingenic/intr.c	8 Mar 2020 20:36:15 -0000
@@ -62,19 +62,31 @@ extern void ingenic_puts(const char *);
  * This is a mask of bits to clear in the SR when we go to a
  * given hardware interrupt priority level.
  */
+#if 0
+        [IPL_NONE] =            0,
+        [IPL_SOFTCLOCK] =       MIPS_SOFT_INT_MASK_0,
+        [IPL_SOFTNET] =         MIPS_SOFT_INT_MASK,
+        [IPL_VM] =              MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0,
+        [IPL_SCHED] =           MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
+                                    | MIPS_INT_MASK_1 | MIPS_INT_MASK_5,
+        [IPL_DDB] =             MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
+                                    | MIPS_INT_MASK_1 | MIPS_INT_MASK_5,
+        [IPL_HIGH] =            MIPS_INT_MASK,
+#endif
+
 static const struct ipl_sr_map ingenic_ipl_sr_map = {
     .sr_bits = {
 	[IPL_NONE] =		0,
 	[IPL_SOFTCLOCK] =	MIPS_SOFT_INT_MASK_0,
-	[IPL_SOFTNET] =		MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
+	[IPL_SOFTNET] =		MIPS_SOFT_INT_MASK,
 	[IPL_VM] =
-	    MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
+	    MIPS_SOFT_INT_MASK |
 	    MIPS_INT_MASK_0 |
 	    MIPS_INT_MASK_3 |
 	    MIPS_INT_MASK_4 |
 	    MIPS_INT_MASK_5,
 	[IPL_SCHED] =
-	    MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
+	    MIPS_SOFT_INT_MASK |
 	    MIPS_INT_MASK_0 |
 	    MIPS_INT_MASK_1 |
 	    MIPS_INT_MASK_2 |
@@ -136,7 +148,9 @@ evbmips_intr_init(void)
 #endif
 	mips_cp0_corereim_write(reg);
 
+#ifdef MULTIPROCESSOR
 	mips_cp0_corembox_write(1, 0);		/* ping the 2nd core */
+#endif
 	DPRINTF("%s %08x\n", __func__, reg);
 }
 
@@ -153,8 +167,12 @@ evbmips_iointr(int ipl, uint32_t ipendin
 	ingenic_puts(buffer);
 #endif
 #endif
+#ifdef MULTIPROCESSOR
 	/* see which core we're on */
-	id = mipsNN_cp0_ebase_read() & 7;
+	id = mips_cp0_ebase_read() & 7;
+#else
+	id = 0;
+#endif
 
 	/*
 	 * XXX
@@ -313,6 +331,15 @@ ingenic_irq(int ipl)
 	writereg(JZ_ICMCR1, hh);
 }
 
+void evbmips_intr_events(void);
+void
+evbmips_intr_events(void)
+{
+	for (size_t i = 0; i < NINTR; i++) {
+		printf("irq %2zu count %llx\n", i, intrs[i].ih_count.ev_count);
+	}
+}
+
 void *
 evbmips_intr_establish(int irq, int (*func)(void *), void *arg)
 {
Index: sys/arch/evbmips/ingenic/machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/ingenic/machdep.c,v
retrieving revision 1.14
diff -u -p -w -b -r1.14 machdep.c
--- sys/arch/evbmips/ingenic/machdep.c	21 May 2017 06:49:12 -0000	1.14
+++ sys/arch/evbmips/ingenic/machdep.c	8 Mar 2020 20:36:15 -0000
@@ -158,6 +158,8 @@ ingenic_send_ipi(struct cpu_info *ci, in
 }
 #endif /* MULTIPROCESSOR */
 
+long long nhstatus;
+int nhedata;
 void
 mach_init(void)
 {
@@ -170,13 +172,105 @@ mach_init(void)
 
 	memset(edata, 0, (char *)kernend - edata);
 
+
+
+#if FREEBSD
+        mips_postboot_fixup();
+
+        /* Initialize pcpu stuff */
+        mips_pcpu0_init();
+
+
+
+
+        for (i = 0; i < 10; i++) {
+                phys_avail[i] = 0;
+        }
+
+        /* The minimal amount of memory Ingenic SoC can have. */
+        dump_avail[0] = phys_avail[0] = MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
+        physmem = realmem = btoc(32 * 1024 * 1024);
+
+        /*
+         * X1000 mips cpu special.
+         * TODO: do anyone know what is this ?
+         */
+        __asm(
+                "li     $2, 0xa9000000  \n\t"
+                "mtc0   $2, $5, 4       \n\t"
+                "nop                    \n\t"
+                ::"r"(2));
+
+
+        init_param1();
+        init_param2(physmem);
+        mips_cpu_init();
+        pmap_bootstrap();
+        mips_proc0_init();
+        mutex_init();
+        kdb_init();
+        led[0] = 0x8000;
+#ifdef KDB
+        if (boothowto & RB_KDB)
+                kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
+#endif
+
+#endif
+
+#if 0
+	/*
+         * flag that some firmware may have left set and the TS bit (for
+         * IP27).  Set XX for ISA IV code to work.
+         */
+        unsigned int status_set = ST0_CU0;
+#ifdef CONFIG_64BIT
+        status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
+#endif
+        if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
+                status_set |= ST0_XX;
+        if (cpu_has_dsp)
+                status_set |= ST0_MX;
+
+        change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
+                         status_set);
+
+
+
+#endif
+
+
+        /* Clear BEV in SR so we start handling our own exceptions */
+        mips_cp0_status_write(mips_cp0_status_read() |
+	    MIPS_SR_COP_0_BIT);
+
+
+
 	/* setup early console */
 	ingenic_putchar_init();
+	uint32_t reg = mips_cp0_corereim_read();
+	reg &= ~REIM_MIRQ0_M;
+	mips_cp0_corereim_write(reg);
+
+	mips_cp0_corembox_write(0, 0);
+	mips_cp0_corembox_write(0, 1);
+
+	uint32_t v = (uint32_t)~CS_MIRQ0_P;
+	mips_cp0_corestatus_write(v);
+
+
+
+
+#ifndef MULTIPROCESSOR
+	mips_vector_init(NULL, false);
+#else
+	mips_vector_init(NULL, true);
+#endif
 
 	/* set CPU model info for sysctl_hw */
 	cpu_setmodel("Ingenic XBurst");
-	mips_vector_init(NULL, false);
+
 	cal_timer();
+
 	uvm_md_init();
 	/*
 	 * Look at arguments passed to us and compute boothowto.
@@ -186,6 +280,9 @@ mach_init(void)
 	boothowto |= RB_KDB;
 #endif
 
+#if 0
+	mach_init_memory(memsize);
+#endif
 	/*
 	 * Determine the memory size.
 	 *
@@ -202,16 +299,26 @@ mach_init(void)
 	 * we can see them through KSEG*
 	 * assume 1GB for now, the SoC can theoretically support up to 3GB
 	 */
+	mem_cluster_cnt = 0;
+
 	mem_clusters[0].start = PAGE_SIZE;
 	mem_clusters[0].size = 0x10000000 - PAGE_SIZE;
+	mem_cluster_cnt++;
+#if 1
 	mem_clusters[1].start = 0x30000000;
 	mem_clusters[1].size = 0x30000000;
-	mem_cluster_cnt = 2;
+	mem_cluster_cnt++;
+#endif
+
+apbus_init();
+	extern char kernel_text[];
+	extern char end[];
 
+	nhstatus = mips_cp0_status_read();
 	/*
 	 * Load the available pages into the VM system.
 	 */
-	mips_page_physload(MIPS_KSEG0_START, (vaddr_t)kernend,
+	mips_page_physload(mips_trunc_page(kernel_text), mips_round_page(end),
 	    mem_clusters, mem_cluster_cnt, NULL, 0);
 
 	/*
Index: sys/arch/hpcmips/vr/vrpiu.c
===================================================================
RCS file: /cvsroot/src/sys/arch/hpcmips/vr/vrpiu.c,v
retrieving revision 1.42
diff -u -p -w -b -r1.42 vrpiu.c
--- sys/arch/hpcmips/vr/vrpiu.c	27 Oct 2012 17:17:56 -0000	1.42
+++ sys/arch/hpcmips/vr/vrpiu.c	8 Mar 2020 20:36:16 -0000
@@ -36,6 +36,7 @@
 __KERNEL_RCSID(0, "$NetBSD: vrpiu.c,v 1.42 2012/10/27 17:17:56 chs Exp $");
 
 #include <sys/param.h>
+#include <sys/bus.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
@@ -45,7 +46,6 @@ __KERNEL_RCSID(0, "$NetBSD: vrpiu.c,v 1.
 #include <dev/wscons/wsconsio.h>
 #include <dev/wscons/wsmousevar.h>
 
-#include <machine/bus.h>
 #include <machine/platid.h>
 #include <machine/platid_mask.h>
 #include <machine/config_hook.h>
@@ -122,7 +122,7 @@ int		vrpiu_ad_enable(void *);
 void		vrpiu_ad_disable(void *);
 static void	vrpiu_start_powerstate(void *);
 static void	vrpiu_calc_powerstate(struct vrpiu_softc *);
-static void	vrpiu_send_battery_event(struct vrpiu_softc *);
+//static void	vrpiu_send_battery_event(struct vrpiu_softc *);
 static void	vrpiu_power(int, void *);
 static u_int	scan_interval(u_int data);
 
@@ -811,6 +811,7 @@ vrpiu_start_powerstate(void *v)
 void
 vrpiu_calc_powerstate(struct vrpiu_softc *sc)
 {
+#if 0
 	extern void vrgiu_diff_io(void);
 	vrpiu_ad_disable(sc);
 	VPRINTF(("vrpiu:AD: %d, %d, %d\n",
@@ -827,6 +828,7 @@ vrpiu_calc_powerstate(struct vrpiu_softc
 		    vrpiu_start_powerstate, sc);
 	if (bootverbose)
 		vrgiu_diff_io();
+#endif
 
 }
 
@@ -846,6 +848,7 @@ vrpiu_power(int why, void *arg)
 	}
 }
 
+#if 0
 static void
 vrpiu_send_battery_event(struct vrpiu_softc *sc)
 {
@@ -912,6 +915,7 @@ vrpiu_send_battery_event(struct vrpiu_so
 	    (void *)&sc->sc_battery);
 #endif /* VRPIU_ADHOC_BATTERY_EVENT */
 }
+#endif
 
 #ifdef DEBUG
 void
Index: sys/arch/mips/cavium/octeonvar.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/cavium/octeonvar.h,v
retrieving revision 1.6
diff -u -p -w -b -r1.6 octeonvar.h
Index: sys/arch/mips/conf/files.ingenic
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/conf/files.ingenic,v
retrieving revision 1.10
diff -u -p -w -b -r1.10 files.ingenic
--- sys/arch/mips/conf/files.ingenic	21 May 2017 06:49:13 -0000	1.10
+++ sys/arch/mips/conf/files.ingenic	8 Mar 2020 20:36:16 -0000
@@ -3,6 +3,9 @@
 file	arch/mips/mips/bus_dma.c
 file	arch/mips/mips/locore_ingenic.S
 
+#file	arch/mips/mips/mips3_clock.c
+#file	arch/mips/mips/mips3_clockintr.c
+
 include "dev/scsipi/files.scsipi"		# SCSI devices
 include "dev/ata/files.ata"			# ATA devices
 include "dev/usb/files.usb"			# USB devices
Index: sys/arch/mips/include/cache.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/cache.h,v
retrieving revision 1.14
diff -u -p -w -b -r1.14 cache.h
--- sys/arch/mips/include/cache.h	18 Aug 2016 22:23:20 -0000	1.14
+++ sys/arch/mips/include/cache.h	8 Mar 2020 20:36:16 -0000
@@ -247,10 +247,6 @@ struct mips_cache_info {
 
 extern struct mips_cache_info mips_cache_info;
 
-
-/*
- * XXX XXX XXX THIS SHOULD NOT EXIST XXX XXX XXX
- */
 #define	mips_cache_indexof(x)	(((vaddr_t)(x)) & MIPS_CACHE_ALIAS_MASK)
 #define	mips_cache_badalias(x,y) (((vaddr_t)(x)^(vaddr_t)(y)) & MIPS_CACHE_ALIAS_MASK)
 
Index: sys/arch/mips/include/locore.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/locore.h,v
retrieving revision 1.104
diff -u -p -w -b -r1.104 locore.h
--- sys/arch/mips/include/locore.h	6 Apr 2019 03:06:26 -0000	1.104
+++ sys/arch/mips/include/locore.h	8 Mar 2020 20:36:16 -0000
@@ -418,6 +418,12 @@ uint32_t mips3_cp0_config_read(void);
 void	mips3_cp0_config_write(uint32_t);
 
 #ifdef MIPSNN
+uint32_t mipsNN_cp0_intctl_read(void);
+void	mipsNN_cp0_intctl_write(uint32_t);
+uint32_t mipsNN_cp0_srsctl_read(void);
+void	mipsNN_cp0_srsctl_write(uint32_t);
+uint32_t mipsNN_cp0_srsmap_read(void);
+void	mipsNN_cp0_srsmap_write(uint32_t);
 uint32_t mipsNN_cp0_config1_read(void);
 void	mipsNN_cp0_config1_write(uint32_t);
 uint32_t mipsNN_cp0_config2_read(void);
Index: sys/arch/mips/mips/bus_dma.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/bus_dma.c,v
retrieving revision 1.38
diff -u -p -w -b -r1.38 bus_dma.c
--- sys/arch/mips/mips/bus_dma.c	17 Aug 2016 22:02:19 -0000	1.38
+++ sys/arch/mips/mips/bus_dma.c	8 Mar 2020 20:36:16 -0000
@@ -889,12 +889,11 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dm
 			struct mips_cache_info * const mci = &mips_cache_info;
 			register_t start = vaddr;
 			register_t end = vaddr + minlen;
-			register_t preboundary, firstboundary, lastboundary;
 			register_t mask = mci->mci_dcache_align_mask;
 
-			preboundary = start & ~mask;
-			firstboundary = (start + mask) & ~mask;
-			lastboundary = end & ~mask;
+			register_t preboundary = start & ~mask;
+			register_t firstboundary = (start + mask) & ~mask;
+			register_t lastboundary = end & ~mask;
 			if (preboundary < start && preboundary < lastboundary)
 				mips_dcache_wbinv_range(preboundary,
 				    mci->mci_dcache_align);
Index: sys/arch/mips/mips/cache.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/cache.c,v
retrieving revision 1.61
diff -u -p -w -b -r1.61 cache.c
--- sys/arch/mips/mips/cache.c	27 Dec 2019 09:47:18 -0000	1.61
+++ sys/arch/mips/mips/cache.c	8 Mar 2020 20:36:16 -0000
@@ -494,11 +494,11 @@ primary_cache_is_2way:
 		case 32:
 			/* used internally by mipsNN_picache_sync_range */
 			mco->mco_intern_icache_sync_range =
-			    cache_r4k_icache_hit_inv_16;
+			    cache_r4k_icache_hit_inv_32;
 
 			/* used internally by mipsNN_picache_sync_range_index */
 			mco->mco_intern_icache_sync_range_index =
-			    cache_r4k_icache_index_inv_16;
+			    cache_r4k_icache_index_inv_32;
 			break;
 
 		default:
@@ -646,6 +646,7 @@ primary_cache_is_2way:
 		 * For current version chips, [the] operating system is
 		 * obliged to eliminate the potential for virtual aliasing.
 		 */
+		// XXXNH
 		uvmexp.ncolors = mci->mci_pdcache_ways;
 		break;
 #endif
@@ -680,9 +681,15 @@ primary_cache_is_2way:
 	}
 
 #if (MIPS2 + MIPS3 + MIPS4) > 0
-	if (mci->mci_cache_virtual_alias) {
-		mci->mci_cache_prefer_mask = mci->mci_pdcache_way_mask;
+	if (mci->mci_cache_virtual_alias ||
+	    mci->mci_icache_virtual_alias) {
+		mci->mci_cache_prefer_mask =
+		    max(mci->mci_pdcache_way_mask, mci->mci_pdcache_way_mask);
+		    //max(mci->mci_pdcache_way_mask, mci->mci_picache_way_mask) - 1;
 
+		mci->mci_cache_alias_mask =
+		    max(mci->mci_cache_alias_mask, mci->mci_cache_alias_mask);
+		    //max(mci->mci_cache_alias_mask, mci->mci_icache_alias_mask);
 		uvmexp.ncolors = (mci->mci_cache_prefer_mask >> PAGE_SHIFT) + 1;
 	}
 #endif
Index: sys/arch/mips/mips/cache_r4k.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/cache_r4k.c,v
retrieving revision 1.14
diff -u -p -w -b -r1.14 cache_r4k.c
--- sys/arch/mips/mips/cache_r4k.c	11 Jul 2016 23:06:54 -0000	1.14
+++ sys/arch/mips/mips/cache_r4k.c	8 Mar 2020 20:36:16 -0000
@@ -71,6 +71,12 @@ r4k_icache_sync_range_generic(register_t
 	mips_intern_icache_sync_range_index(va, size);
 }
 
+#define	round_line(x,n)		(((x) + (register_t)(n) - 1) & -(register_t)(n))
+#define	trunc_line(x,n)		((x) & -(register_t)(n))
+
+int r4k_icache_cnt1;
+int r4k_icache_cnt2;
+
 void
 r4k_icache_sync_range_index_generic(vaddr_t va, vsize_t size)
 {
@@ -82,9 +88,24 @@ r4k_icache_sync_range_index_generic(vadd
 	 * bits that determine the cache index, and make a KSEG0
 	 * address out of them.
 	 */
-	va = MIPS_PHYS_TO_KSEG0(va & mips_cache_info.mci_picache_way_mask);
-	size &= mips_cache_info.mci_picache_way_mask;
+	struct mips_cache_info * const mci = &mips_cache_info;
+	const size_t line_size = mci->mci_picache_line_size;
+	const size_t way_size = mci->mci_picache_way_size;
+	const size_t way_mask = mci->mci_picache_way_mask;
+	vaddr_t eva;
+
+	va = MIPS_PHYS_TO_KSEG0(va & way_mask);
 
+	eva = round_line(va + size, line_size);
+	va = trunc_line(va, line_size);
+	size = eva - va;
+
+	if (size >= way_size) {
+		r4k_icache_cnt2++;
+		r4k_icache_sync_all_generic();
+		return;
+	}
+	r4k_icache_cnt1++;
 	mips_intern_icache_sync_range_index(va, size);
 }
 
Index: sys/arch/mips/mips/cache_r5k.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/cache_r5k.c,v
retrieving revision 1.20
diff -u -p -w -b -r1.20 cache_r5k.c
--- sys/arch/mips/mips/cache_r5k.c	27 Apr 2017 20:05:09 -0000	1.20
+++ sys/arch/mips/mips/cache_r5k.c	8 Mar 2020 20:36:16 -0000
@@ -117,7 +117,7 @@ r5k_picache_sync_range_index(vaddr_t va,
 	const size_t ways = mci->mci_picache_ways;
 	const size_t line_size = mci->mci_picache_line_size;
 	const size_t way_size = mci->mci_picache_way_size;
-	const size_t way_mask = way_size - 1;
+	const size_t way_mask = mci->mci_picache_way_mask;
 	vaddr_t eva;
 
 	/*
Index: sys/arch/mips/mips/db_disasm.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/db_disasm.c,v
retrieving revision 1.32
diff -u -p -w -b -r1.32 db_disasm.c
Index: sys/arch/mips/mips/locore_mips1.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/locore_mips1.S,v
retrieving revision 1.93
diff -u -p -w -b -r1.93 locore_mips1.S
--- sys/arch/mips/mips/locore_mips1.S	8 Jun 2017 05:46:57 -0000	1.93
+++ sys/arch/mips/mips/locore_mips1.S	8 Mar 2020 20:36:16 -0000
@@ -667,6 +667,8 @@ NESTED_NOPROFILE(MIPSX(user_gen_exceptio
 #endif
 	move	sp, k0				# switch to kernel SP
 	move	MIPS_CURLWP, k1
+
+	/* XXXNH re-enable interrupts before calling trap for NOFPU case */
 #ifndef NOFPU
 	lui	t0, %hi(MIPS_SR_COP_1_BIT)
 	and	t0, a0
Index: sys/arch/mips/mips/locore_mips3.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/locore_mips3.S,v
retrieving revision 1.114
diff -u -p -w -b -r1.114 locore_mips3.S
--- sys/arch/mips/mips/locore_mips3.S	26 Jan 2018 05:29:43 -0000	1.114
+++ sys/arch/mips/mips/locore_mips3.S	8 Mar 2020 20:36:16 -0000
@@ -264,6 +264,70 @@ END(mips3_cp0_config_write)
 #else
 	.set mips64
 #endif
+
+/*
+ * uint32_t mipsNN_cp0_intctl_read(void)
+ *
+ *	Return the current value of the CP0 Interrupt system status and control register.
+ */
+LEAF(mipsNN_cp0_intctl_read)
+	mfc0	v0, MIPS_COP_0_INTCTL
+	jr	ra
+	 nop
+END(mipsNN_cp0_intctl_read)
+
+/*
+ * void mipsNN_cp0_intctl_write(uint32_t)
+ *
+ *	Set the value of the CP0 Interrupt system status and control register.
+ */
+LEAF(mipsNN_cp0_intctl_write)
+	mtc0	a0, MIPS_COP_0_INTCTL
+	JR_HB_RA
+END(mipsNN_cp0_intctl_write)
+
+/*
+ * uint32_t mipsNN_cp0_srsctl_read(void)
+ *
+ *	Return the current value of the CP0 Shadow register set status and control register.
+ */
+LEAF(mipsNN_cp0_srsctl_read)
+	mfc0	v0, MIPS_COP_0_SRSCTL
+	jr	ra
+	 nop
+END(mipsNN_cp0_srsctl_read)
+
+/*
+ * void mipsNN_cp0_srsctl_write(uint32_t)
+ *
+ *	Set the value of the CP0 Shadow register set status and control register.
+ */
+LEAF(mipsNN_cp0_srsctl_write)
+	mtc0	a0, MIPS_COP_0_SRSCTL
+	JR_HB_RA
+END(mipsNN_cp0_srsctl_write)
+
+/*
+ * uint32_t mipsNN_cp0_srsmap_read(void)
+ *
+ *	Return the current value of the CP0 Shadow set IPL mapping register.
+ */
+LEAF(mipsNN_cp0_srsmap_read)
+	mfc0	v0, MIPS_COP_0_SRSMAP
+	jr	ra
+	 nop
+END(mipsNN_cp0_srsmap_read)
+
+/*
+ * void mipsNN_cp0_srsmap_write(uint32_t)
+ *
+ *	Set the value of the CP0 Shadow set IPL mapping register.
+ */
+LEAF(mipsNN_cp0_srsmap_write)
+	mtc0	a0, MIPS_COP_0_SRSMAP
+	JR_HB_RA
+END(mipsNN_cp0_srsmap_write)
+
 /*
  * uint32_t mipsNN_cp0_config1_read(void)
  *
@@ -352,6 +416,16 @@ LEAF(mipsNN_cp0_config7_read)
 END(mipsNN_cp0_config7_read)
 
 /*
+ * uint32_t mipsNN_cp0_config7_write(uint32_t)
+ *
+ *	Set the current value of the CP0 Config (Select 7) register.
+ */
+LEAF(mipsNN_cp0_config7_write)
+	mtc0	v0, MIPS_COP_0_CONFIG, 7
+	JR_HB_RA
+END(mipsNN_cp0_config7_write)
+
+/*
  * uintptr_t mipsNN_cp0_watchlo_read(u_int sel)
  *
  *	Return the current value of the selected CP0 Watchlo register.
@@ -485,7 +559,11 @@ END(mipsNN_cp0_ebase_read)
  *	Set the value of the CP0 EBASE (PRID, select 1) register.
  */
 LEAF(mipsNN_cp0_ebase_write)
+#if 0
 	and	v0, v0, 0x1ff
+#else
+	li	v0, 0
+#endif
 	xor	v0, v0, a0
 	jr	ra
 	 mtc0	v0, MIPS_COP_0_EBASE
@@ -635,6 +713,7 @@ LEAF(badaddr64)
 	PTR_L	v1, L_PCB(MIPS_CURLWP)
 	PTR_LA	v0, _C_LABEL(baderr64)
 
+	// XXX !defined???
 #ifdef __mips_o32
 	/* Enable KX */
 	mfc0	t0, MIPS_COP_0_STATUS
Index: sys/arch/mips/mips/mipsX_subr.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mipsX_subr.S,v
retrieving revision 1.107
diff -u -p -w -b -r1.107 mipsX_subr.S
--- sys/arch/mips/mips/mipsX_subr.S	15 Feb 2020 17:01:00 -0000	1.107
+++ sys/arch/mips/mips/mipsX_subr.S	8 Mar 2020 20:36:16 -0000
@@ -420,6 +420,30 @@ VECTOR(MIPSX(tlb_miss), unknown)
 	 PTR_SRA k0, SEGSHIFT - PTR_SCALESHIFT	#03: k0=seg offset (almost)
 #endif
 #else
+
+
+
+//return stp->seg_tab[(va >> SEGSHIFT) & (PMAP_SEGTABSIZE - 1)];
+//XXXNH
+#if 0
+#define NBPG 8192
+#define SEGSHIFT 24
+#define SEGOFSET 16777215
+#define SEGLENGTH 7
+#define NBSEG 16777216
+#define NSEGPG 128
+#define PTPSHIFT 2
+#define PTPLENGTH 11
+#define NPTEPG 2048
+#define XSEGSHIFT 24
+#define XSEGLENGTH 7
+#define USPACE 8192
+
+
+
+#endif
+
+
 	bgez	k0, 1f				#02: k0<0 -> kernel access
 #ifdef MIPSNNR2
 	 _EXT	k0, k0, SEGSHIFT, SEGLENGTH	#03: k0=seg index
@@ -443,6 +467,9 @@ MIPSX(tlb_miss_common):
 	PTR_ADDU k1, k0				#08: k1=seg entry address
 #endif
 	PTR_L	k1, 0(k1)			#09: k1=seg entry
+
+
+// XXXNH
 	_MFC0	k0, MIPS_COP_0_BAD_VADDR	#0a: k0=bad address (again)
 	beqz	k1, MIPSX(nopagetable)		#0b: ==0 -- no page table
 	 # delay slot varies
@@ -488,19 +515,30 @@ MIPSX(tlb_miss_common):
 #endif
 #endif /* PGSHIFT & 1 */
 	_MTC0	k0, MIPS_COP_0_TLB_LO0		#15: lo0 is loaded
+	sll	$0, $0, 3			#17: standard nop (ehb)
+	ehb
+
 	_MTC0	k1, MIPS_COP_0_TLB_LO1		#16: lo1 is loaded
 	sll	$0, $0, 3			#17: standard nop (ehb)
+	sll	$0, $0, 3			#17: standard nop (ehb)
+	ehb
 #ifdef MIPS3
 	nop					#18: extra nop for QED5230
 #endif
 	tlbwr					#19: write to tlb
 	sll	$0, $0, 3			#1a: standard nop (ehb)
-#if (MIPS3 + MIPS64 + MIPS64R2) > 0
+#if 1
+	nop
+//	nop
+	nop
+#else
+#if (MIPS3 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
 	lui	k1, %hi(CPUVAR(EV_TLBMISSES))	#1b: k1=hi of tlbmisses
 	REG_L	k0, %lo(CPUVAR(EV_TLBMISSES))(k1) #1c
 	REG_ADDU k0, 1				#1d
 	REG_S	k0, %lo(CPUVAR(EV_TLBMISSES))(k1) #1e
 #endif
+#endif
 	eret					#1f: return from exception
 	.set	at
 #ifdef MIPS3_LOONGSON2
@@ -1333,6 +1371,7 @@ NESTED_NOPROFILE(MIPSX(user_reserved_ins
 	MFC0_HAZARD
 	PTR_ADDIU v0, 4
 	_MTC0	v0, MIPS_COP_0_EXC_PC
+// Why isn't this ehb???
 	COP0_SYNC
 
 	PTR_L	v1, L_PRIVATE(k1)		# rdhwr $3,$29 updates v1
@@ -1916,6 +1955,7 @@ LEAF_NOPROFILE(MIPSX(kern_tlb_invalid_ex
 	_SRL	k0, k0, WIRED_SHIFT
 #endif
 	_MTC0	k0, MIPS_COP_0_TLB_LO0		# load PTE entry
+	COP0_SYNC
 	and	k0, k0, MIPS3_PG_V		# check for valid entry
 #ifdef MIPS3
 	nop					# required for QED5230
@@ -1931,7 +1971,14 @@ LEAF_NOPROFILE(MIPSX(kern_tlb_invalid_ex
 	_SLL	k0, k0, WIRED_SHIFT
 	_SRL	k0, k0, WIRED_SHIFT
 #endif
-#if UPAGES == 1
+
+
+
+
+
+
+	// XXXNH wtf??? should it be != 1??? or just removed???
+#if UPAGES != 1
 	sltiu	k1, k1, MIPS3_TLB_WIRED_UPAGES	# Luckily this is MIPS3_PG_G
 	or	k1, k1, k0
 #endif
@@ -1970,6 +2017,7 @@ MIPSX(kern_tlbi_odd):
 	 nop					# - delay slot -
 
 	INT_L	k0, -4(k1)			# get even PTE entry
+//	  nop???
 	mfc0	k1, MIPS_COP_0_TLB_INDEX
 #ifdef MIPSNNR2
 	_EXT	k0, k0, 0, WIRED_POS
@@ -1977,7 +2025,13 @@ MIPSX(kern_tlbi_odd):
 	_SLL	k0, k0, WIRED_SHIFT
 	_SRL	k0, k0, WIRED_SHIFT
 #endif
-#if UPAGES == 1
+
+
+
+
+
+	// XXXNH wtf??? should it be != 1??? or just removed???
+#if UPAGES != 1
 	sltiu	k1, k1, MIPS3_TLB_WIRED_UPAGES	# Luckily this is MIPS3_PG_G
 	or	k1, k1, k0
 #endif
@@ -2051,6 +2105,7 @@ END(MIPSX(tlb_get_asid))
 LEAF(MIPSX(tlb_set_asid))
 	_MFC0	v0, MIPS_COP_0_TLB_HI		# read the hi reg value
 #ifdef MIPSNNR2
+	MFC0_HAZARD
 	_INS	v0, a0, V_MIPS3_PG_ASID, S_MIPS3_PG_ASID
 #else
 	li	t0, MIPS3_PG_ASID
@@ -2114,6 +2169,7 @@ LEAF(MIPSX(tlb_update_addr))
 	_SRL	a1, a2, WIRED_SHIFT
 #endif
 	mfc0	v1, MIPS_COP_0_TLB_INDEX	# See what we got
+	MFC0_HAZARD
 #ifdef MIPS3
 	nop
 	nop					# required for QED5230
@@ -2146,6 +2202,7 @@ LEAF(MIPSX(tlb_update_addr))
 1:
 # ODD
 	_MTC0	a1, MIPS_COP_0_TLB_LO1		# init low reg1.
+	// More nops???
 2:
 	COP0_SYNC
 	tlbwi					# update slot found
@@ -2210,8 +2267,12 @@ END(MIPSX(tlb_update_addr))
  *--------------------------------------------------------------------------
  */
 LEAF(MIPSX(tlb_read_entry))
+#ifdef MIPSNNR2
+	di	v1				# Disable interrupts
+#else
 	mfc0	v1, MIPS_COP_0_STATUS		# Save the status register.
 	mtc0	zero, MIPS_COP_0_STATUS		# Disable interrupts
+#endif
 	COP0_SYNC
 #ifdef MIPS3
 	nop
@@ -2259,8 +2320,12 @@ END(MIPSX(tlb_read_entry))
  *--------------------------------------------------------------------------
  */
 LEAF_NOPROFILE(MIPSX(tlb_invalidate_addr))
+#ifdef MIPSNNR2
+	di	ta0				# Disable interrupts
+#else
 	mfc0	ta0, MIPS_COP_0_STATUS		# save status register
 	mtc0	zero, MIPS_COP_0_STATUS		# disable interrupts
+#endif
 	COP0_SYNC
 
 #if (PGSHIFT & 1) == 0
@@ -2277,6 +2342,9 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_addr
 	or	a0, a0, a1
 #endif
 	_MFC0	ta1, MIPS_COP_0_TLB_HI		# save current ASID
+
+	# Not needed as we don't change it
+	#
 	mfc0	ta2, MIPS_COP_0_TLB_PG_MASK	# save current pgMask
 	_MTC0	a0, MIPS_COP_0_TLB_HI		# look for the vaddr & ASID
 	COP0_SYNC
@@ -2288,9 +2356,10 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_addr
 	 li	t2, MIPS_KSEG0_START		# invalid address
 	PTR_SLL	v0, PGSHIFT | 1			# PAGE_SHIFT | 1
 	PTR_ADDU t2, v0
+#if (PGSHIFT & 1) != 0
 	move	t0, zero
 	move	t1, zero
-#if (PGSHIFT & 1) == 0
+#else
 	tlbr					# read entry
 	COP0_SYNC
 	_MFC0	t0, MIPS_COP_0_TLB_LO0		# fetch entryLo0
@@ -2342,6 +2411,8 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_addr
 	nop
 #endif
 2:
+	# PG_MASK because tlbr can change it
+	#
 	mtc0	ta2, MIPS_COP_0_TLB_PG_MASK	# restore pgMask
 	_MTC0	ta1, MIPS_COP_0_TLB_HI		# restore current ASID
 	COP0_SYNC
@@ -2357,35 +2428,39 @@ END(MIPSX(tlb_invalidate_addr))
  * marked global intact.
  */
 LEAF_NOPROFILE(MIPSX(tlb_invalidate_asids))
+#ifdef MIPSNNR2
+	di	v1				# Disable interrupts
+#else
 	mfc0	v1, MIPS_COP_0_STATUS		# save status register
 	mtc0	zero, MIPS_COP_0_STATUS		# disable interrupts
+#endif
 	COP0_SYNC
 
 	_MFC0	t0, MIPS_COP_0_TLB_HI		# Save the current ASID.
-	mfc0	t1, MIPS_COP_0_TLB_WIRED
+	mfc0	t1, MIPS_COP_0_TLB_PG_MASK	# save current pgMask
+	mfc0	t2, MIPS_COP_0_TLB_WIRED
+	INT_L	t3, _C_LABEL(mips_options) + MO_NUM_TLB_ENTRIES
 	li	v0, MIPS_KSEG0_START		# invalid address
-	INT_L	t2, _C_LABEL(mips_options) + MO_NUM_TLB_ENTRIES
-	mfc0	t3, MIPS_COP_0_TLB_PG_MASK	# save current pgMask
 
-	# do {} while (t1 < t2)
+	# do {} while (t2 < t3)
 1:
-	mtc0	t1, MIPS_COP_0_TLB_INDEX	# set index
+	mtc0	t2, MIPS_COP_0_TLB_INDEX	# set index
 	COP0_SYNC
-	sll	ta0, t1, PGSHIFT | 1		# PAGE_SHIFT | 1
+	sll	ta0, t2, PGSHIFT | 1		# PAGE_SHIFT | 1
 	tlbr					# obtain an entry
 	COP0_SYNC
-	_MFC0	ta1, MIPS_COP_0_TLB_LO1
+	_MFC0	a2, MIPS_COP_0_TLB_LO1
 	MFC0_HAZARD
-	and	ta1, MIPS3_PG_G			# check to see it has G bit
-	bnez	ta1, 2f				# yep, skip this one.
+	and	a2, MIPS3_PG_G			# check to see it has G bit
+	bnez	a2, 2f				# yep, skip this one.
 	 nop
-	_MFC0	ta1, MIPS_COP_0_TLB_HI		# get VA and ASID
+	_MFC0	a2, MIPS_COP_0_TLB_HI		# get VA and ASID
 	MFC0_HAZARD
-	and	ta1, MIPS3_PG_ASID		# focus on ASID
-	sltu	a3, ta1, a0			# asid < base?
+	and	a2, MIPS3_PG_ASID		# focus on ASID
+	sltu	a3, a2, a0			# asid < base?
 	bnez	a3, 2f				# yes, skip this entry.
 	 nop
-	sltu	a3, a1, ta1			# limit < asid
+	sltu	a3, a1, a2			# limit < asid
 	bnez	a3, 2f				# yes, skip this entry.
 	 nop
 	PTR_ADDU ta0, v0
@@ -2393,17 +2468,19 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_asid
 	_MTC0	ta0, MIPS_COP_0_TLB_HI		# make entryHi invalid
 	_MTC0	zero, MIPS_COP_0_TLB_LO0	# zero out entryLo0
 	_MTC0	zero, MIPS_COP_0_TLB_LO1	# zero out entryLo1
+#if 0
 	mtc0	zero, MIPS_COP_0_TLB_PG_MASK	# zero out mask entry
+#endif
 	COP0_SYNC
 	tlbwi					# invalidate the TLB entry
 	COP0_SYNC
 2:
-	addu	t1, 1
-	bne	t1, t2, 1b
+	addu	t2, 1
+	bne	t2, t3, 1b
 	 nop
 
 	_MTC0	t0, MIPS_COP_0_TLB_HI		# restore ASID.
-	mtc0	t3, MIPS_COP_0_TLB_PG_MASK	# restore pgMask
+	mtc0	t1, MIPS_COP_0_TLB_PG_MASK	# restore pgMask
 	COP0_SYNC
 
 #ifdef MIPS3_LOONGSON2
@@ -2423,8 +2500,12 @@ END(MIPSX(tlb_invalidate_asids))
  * leaving entries for user space (not marked global) intact.
  */
 LEAF_NOPROFILE(MIPSX(tlb_invalidate_globals))
+#ifdef MIPSNNR2
+	di	v1				# Disable interrupts
+#else
 	mfc0	v1, MIPS_COP_0_STATUS		# save status register
 	mtc0	zero, MIPS_COP_0_STATUS		# disable interrupts
+#endif
 	COP0_SYNC
 
 	_MFC0	t0, MIPS_COP_0_TLB_HI		# save current ASID
@@ -2450,7 +2531,9 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_glob
 	_MTC0	ta0, MIPS_COP_0_TLB_HI		# make entryHi invalid
 	_MTC0	zero, MIPS_COP_0_TLB_LO0	# zero out entryLo0
 	_MTC0	zero, MIPS_COP_0_TLB_LO1	# zero out entryLo1
+#if 0
 	mtc0	zero, MIPS_COP_0_TLB_PG_MASK	# zero out mask entry
+#endif
 	COP0_SYNC
 	tlbwi					# invalidate the TLB entry
 	COP0_SYNC
@@ -2479,8 +2562,12 @@ END(MIPSX(tlb_invalidate_globals))
  * Invalidate all of non-wired TLB entries.
  */
 LEAF_NOPROFILE(MIPSX(tlb_invalidate_all))
+#ifdef MIPSNNR2
+	di	ta0				# Disable interrupts
+#else
 	mfc0	ta0, MIPS_COP_0_STATUS		# save status register
 	mtc0	zero, MIPS_COP_0_STATUS		# disable interrupts
+#endif
 	COP0_SYNC
 
 	INT_L	a0, _C_LABEL(mips_options) + MO_NUM_TLB_ENTRIES
@@ -2713,18 +2800,6 @@ END(MIPSX(lwp_trampoline))
 
 LEAF_NOPROFILE(MIPSX(cpu_switch_resume))
 #if (PGSHIFT < 14)
-#if (USPACE > PAGE_SIZE) || !defined(_LP64)
-	INT_L	a1, L_MD_UPTE_0(a0)		# a1 = upte[0]
-#if (PGSHIFT & 1)
-#if (USPACE > PAGE_SIZE)
-#error Unsupported
-#else
-	/* even/odd are contiguaous */
-	INT_ADD a2, a1, MIPS3_PG_NEXT		# a2 = upper half
-#endif
-#else
-	INT_L	a2, L_MD_UPTE_1(a0)		# a2 = upte[1]
-#endif /* (PGSHIFT & 1) */
 	PTR_L	v0, L_PCB(a0)			# va = l->l_addr
 #if VM_MIN_KERNEL_ADDRESS == MIPS_KSEG2_START
 	li	t0, VM_MIN_KERNEL_ADDRESS	# compute index
@@ -2740,6 +2815,7 @@ LEAF_NOPROFILE(MIPSX(cpu_switch_resume))
 	 nop
 #endif
 
+#ifdef DIAGNOSTIC
 #if (PGSHIFT & 1) == 0
 	and	t0, v0, MIPS3_PG_ODDPG
 	beqz	t0, MIPSX(entry0)
@@ -2751,9 +2827,26 @@ LEAF_NOPROFILE(MIPSX(cpu_switch_resume))
 
 MIPSX(entry0):
 #endif /* (PGSHIFT & 1) == 0 */
+#endif /* DIAGNOSTIC */
+
+#if (USPACE > PAGE_SIZE) || !defined(_LP64)
+	INT_L	a1, L_MD_UPTE_0(a0)		# a1 = upte[0]
+#if (PGSHIFT & 1)
+#if (USPACE > PAGE_SIZE)
+#error Unsupported
+#else
+	/* even/odd are contiguaous */
+	INT_ADD a2, a1, MIPS3_PG_NEXT		# a2 = upper half
+#endif
+#else
+	INT_L	a2, L_MD_UPTE_1(a0)		# a2 = upte[1]
+#endif /* (PGSHIFT & 1) */
 	_MFC0	ta1, MIPS_COP_0_TLB_HI		# save TLB_HI
 	_MTC0	v0, MIPS_COP_0_TLB_HI		# VPN = va
 
+
+// XXXNH save PGMASK!?!???!!!
+
 	COP0_SYNC
 	tlbp					# probe VPN
 	COP0_SYNC
@@ -2793,6 +2886,7 @@ MIPSX(resume):
 #ifdef MIPSNNR2
 	PTR_L	v0, L_PRIVATE(a0)		# get lwp private
 	_MTC0	v0, MIPS_COP_0_USERLOCAL	# make available for rdhwr
+	COP0_SYNC
 #endif
 	jr	ra
 	 nop
Index: sys/arch/mips/mips/pmap_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/pmap_machdep.c,v
retrieving revision 1.26
diff -u -p -w -b -r1.26 pmap_machdep.c
--- sys/arch/mips/mips/pmap_machdep.c	20 Oct 2019 08:29:38 -0000	1.26
+++ sys/arch/mips/mips/pmap_machdep.c	8 Mar 2020 20:36:16 -0000
@@ -165,9 +165,28 @@ PMAP_COUNTER(zeroed_pages, "pages zeroed
 PMAP_COUNTER(copied_pages, "pages copied");
 extern struct evcnt pmap_evcnt_page_cache_evictions;
 
+int nhdebug1 = 1;
 u_int pmap_page_cache_alias_mask;
 
-#define pmap_md_cache_indexof(x)	(((vaddr_t)(x)) & pmap_page_cache_alias_mask)
+static inline int
+pmap_md_cache_badalias(vaddr_t va1, vaddr_t va2, int prot)
+{
+	const u_int dmask = mips_cache_info.mci_cache_alias_mask;
+	const u_int imask = pmap_page_cache_alias_mask;
+	u_int aliasmask = prot & VM_PROT_EXECUTE ?  imask : dmask;
+
+	return (va1 ^ va2) & aliasmask;
+}
+
+static inline vaddr_t
+pmap_md_cache_indexof(vaddr_t va, int prot)
+{
+	const u_int dmask = mips_cache_info.mci_cache_alias_mask;
+	const u_int imask = pmap_page_cache_alias_mask;
+	u_int aliasmask = prot & VM_PROT_EXECUTE ?  imask : dmask;
+
+	return va & aliasmask;
+}
 
 static register_t
 pmap_md_map_ephemeral_page(struct vm_page *pg, bool locked_p, int prot,
@@ -184,7 +203,7 @@ pmap_md_map_ephemeral_page(struct vm_pag
 
 	KASSERT(!locked_p || VM_PAGEMD_PVLIST_LOCKED_P(mdpg));
 
-	if (!MIPS_CACHE_VIRTUAL_ALIAS || !mips_cache_badalias(pv->pv_va, pa)) {
+	if (!MIPS_CACHE_VIRTUAL_ALIAS || !pmap_md_cache_badalias(pv->pv_va, pa, prot)) {
 #ifdef _LP64
 		va = MIPS_PHYS_TO_XKPHYS_CACHED(pa);
 #else
@@ -193,6 +212,10 @@ pmap_md_map_ephemeral_page(struct vm_pag
 		}
 #endif
 	}
+	UVMHIST_LOG(pmaphist, "    pv_va %#"PRIxVADDR " pa %#"PRIxVADDR
+	    " va %#"PRIxVADDR " %#x kseg", pv->pv_va, pa, va,
+	    pmap_md_cache_badalias(pv->pv_va, pa, prot));
+
 	if (va == 0) {
 		/*
 		 * Make sure to use a congruent mapping to the last mapped
@@ -200,22 +223,23 @@ pmap_md_map_ephemeral_page(struct vm_pag
 		 */
 		kpreempt_disable(); // paired with the one in unmap
 		struct cpu_info * const ci = curcpu();
-		if (MIPS_CACHE_VIRTUAL_ALIAS) {
 			KASSERT(ci->ci_pmap_dstbase != 0);
 			KASSERT(ci->ci_pmap_srcbase != 0);
 
+		if (MIPS_CACHE_VIRTUAL_ALIAS) {
 			const u_int __diagused mask = pmap_page_cache_alias_mask;
 			KASSERTMSG((ci->ci_pmap_dstbase & mask) == 0,
 			    "%#"PRIxVADDR, ci->ci_pmap_dstbase);
 			KASSERTMSG((ci->ci_pmap_srcbase & mask) == 0,
 			    "%#"PRIxVADDR, ci->ci_pmap_srcbase);
 		}
+
 		vaddr_t nva = (prot & VM_PROT_WRITE
 			? ci->ci_pmap_dstbase
 			: ci->ci_pmap_srcbase)
 		    + pmap_md_cache_indexof(MIPS_CACHE_VIRTUAL_ALIAS
 			? pv->pv_va
-			: pa);
+			: pa, prot);
 
 		va = (intptr_t)nva;
 		/*
@@ -232,7 +256,20 @@ pmap_md_map_ephemeral_page(struct vm_pag
 		rv = tlb_update_addr(va, KERNEL_PID, npte, true);
 		KASSERTMSG(rv == 1, "va %#"PRIxREGISTER" pte=%#"PRIxPTE" rv=%d",
 		    va, pte_value(npte), rv);
+
+		UVMHIST_LOG(pmaphist, "    pv_va %#"PRIxVADDR " va %#"PRIxVADDR
+		    " index %x pmap_base %x", pv->pv_va, va,
+		    pmap_md_cache_indexof(MIPS_CACHE_VIRTUAL_ALIAS ? pv->pv_va : pa, prot),
+		    (prot & VM_PROT_WRITE ? ci->ci_pmap_dstbase : ci->ci_pmap_srcbase));
+
+		KASSERTMSG(!pmap_md_cache_badalias(pv->pv_va, va, prot), "pv_va %#"PRIxVADDR
+		    " va %#"PRIxVADDR " index %"PRIxVADDR " pmap_base %"PRIxVADDR,
+		    pv->pv_va, va,
+		    pmap_md_cache_indexof(MIPS_CACHE_VIRTUAL_ALIAS ? pv->pv_va : pa, prot),
+		    (prot & VM_PROT_WRITE ? ci->ci_pmap_dstbase : ci->ci_pmap_srcbase));
 	}
+
+	UVMHIST_LOG(pmaphist, "    pv_va %#"PRIxVADDR " pa %#"PRIxVADDR " phys", pv->pv_va, pa, 0, 0);
 	if (MIPS_CACHE_VIRTUAL_ALIAS) {
 		/*
 		 * If we are forced to use an incompatible alias, flush the
@@ -240,16 +277,13 @@ pmap_md_map_ephemeral_page(struct vm_pag
 		 */
 		if (!locked_p)
 			(void)VM_PAGEMD_PVLIST_READLOCK(mdpg);
-		if (VM_PAGEMD_CACHED_P(mdpg)
-		    && mips_cache_badalias(pv->pv_va, va)) {
-			register_t ova = (intptr_t)trunc_page(pv->pv_va);
-			mips_dcache_wbinv_range_index(ova, PAGE_SIZE);
-			/*
-			 * If there is no active mapping, remember this new one.
-			 */
-			if (pv->pv_pmap == NULL)
-				pv->pv_va = va;
-		}
+
+		// The code above works hard to get us a 'va' that is not an alias with
+		// old va, so HTF does this fire?
+
+		KASSERTMSG(!pmap_md_cache_badalias(pv->pv_va, va, prot), "last va %"PRIxVADDR
+		    " va %#"PRIxVADDR, pv->pv_va, va);
+
 		if (!locked_p)
 			VM_PAGEMD_PVLIST_UNLOCK(mdpg);
 	}
@@ -264,7 +298,7 @@ pmap_md_unmap_ephemeral_page(struct vm_p
 	pt_entry_t old_pte)
 {
 	struct vm_page_md * const mdpg = VM_PAGE_TO_MD(pg);
-	pv_entry_t pv = &mdpg->mdpg_first;
+	//pv_entry_t pv = &mdpg->mdpg_first;
 
 	UVMHIST_FUNC(__func__); UVMHIST_CALLED(pmaphist);
 	UVMHIST_LOG(pmaphist, "(pg=%p, va=%#lx, pte=%#"PRIxPTE")",
@@ -275,15 +309,12 @@ pmap_md_unmap_ephemeral_page(struct vm_p
 	if (MIPS_CACHE_VIRTUAL_ALIAS) {
 		if (!locked_p)
 			(void)VM_PAGEMD_PVLIST_READLOCK(mdpg);
-		/*
-		 * If this page was previously uncached or we had to use an
-		 * incompatible alias, flush it from the cache.
-		 */
-		if (VM_PAGEMD_UNCACHED_P(mdpg)
-		    || (pv->pv_pmap != NULL
-			&& mips_cache_badalias(pv->pv_va, va))) {
-			mips_dcache_wbinv_range(va, PAGE_SIZE);
-		}
+
+#if 0
+		KASSERTMSG(!pmap_md_cache_badalias(pv->pv_va, va, prot), "last va %"PRIxVADDR
+		    " va %#"PRIxVADDR, pv->pv_va, va);
+#endif
+
 		if (!locked_p)
 			VM_PAGEMD_PVLIST_UNLOCK(mdpg);
 	}
@@ -313,9 +344,11 @@ pmap_md_vca_page_wbinv(struct vm_page *p
 	const register_t va = pmap_md_map_ephemeral_page(pg, locked_p,
 	    VM_PROT_READ, &pte);
 
+	UVMHIST_LOG(pmaphist, "  va %#"PRIxVADDR, va, 0, 0, 0);
 	mips_dcache_wbinv_range(va, PAGE_SIZE);
 
 	pmap_md_unmap_ephemeral_page(pg, locked_p, va, pte);
+	UVMHIST_LOG(pmaphist, " <-- done", 0, 0, 0, 0);
 }
 
 bool
@@ -543,27 +576,6 @@ void
 pmap_md_init(void)
 {
 	pmap_md_alloc_ephemeral_address_space(curcpu());
-
-#if defined(MIPS3) && 0
-	if (MIPS_HAS_R4K_MMU) {
-		/*
-		 * XXX
-		 * Disable sosend_loan() in src/sys/kern/uipc_socket.c
-		 * on MIPS3 CPUs to avoid possible virtual cache aliases
-		 * and uncached mappings in pmap_enter_pv().
-		 *
-		 * Ideally, read only shared mapping won't cause aliases
-		 * so pmap_enter_pv() should handle any shared read only
-		 * mappings without uncached ops like ARM pmap.
-		 *
-		 * On the other hand, R4000 and R4400 have the virtual
-		 * coherency exceptions which will happen even on read only
-		 * mappings, so we always have to disable sosend_loan()
-		 * on such CPUs.
-		 */
-		sock_loan_thresh = -1;
-	}
-#endif
 }
 
 /*
@@ -573,6 +585,9 @@ void
 pmap_procwr(struct proc *p, vaddr_t va, size_t len)
 {
 	if (MIPS_HAS_R4K_MMU) {
+#if 1
+// Why do this at all?
+// cf. ARM PMAP changes.
 		/*
 		 * XXX
 		 * shouldn't need to do this for physical d$?
@@ -584,6 +599,7 @@ pmap_procwr(struct proc *p, vaddr_t va, 
 			mips_icache_sync_range((intptr_t)va, len);
 		else
 			mips_icache_sync_range_index((intptr_t)va, len);
+#endif
 	} else {
 		pmap_t pmap = p->p_vmspace->vm_map.pmap;
 		kpreempt_disable();
@@ -678,7 +694,7 @@ pmap_md_page_syncicache(struct vm_page *
 			/* This was probably mapped cached by UBC so flush it */
 			pt_entry_t pte;
 			const register_t tva = pmap_md_map_ephemeral_page(pg, false,
-			    VM_PROT_READ, &pte);
+			    VM_PROT_READ|VM_PROT_EXECUTE, &pte);
 
 			UVMHIST_LOG(pmaphist, "  va %#"PRIxVADDR, tva, 0, 0, 0);
 			mips_dcache_wbinv_range(tva, PAGE_SIZE);
@@ -716,6 +732,7 @@ pmap_md_alloc_poolpage(int flags)
 vaddr_t
 pmap_md_map_poolpage(paddr_t pa, size_t len)
 {
+	UVMHIST_FUNC(__func__); UVMHIST_CALLED(pmaphist);
 
 	struct vm_page * const pg = PHYS_TO_VM_PAGE(pa);
 	vaddr_t va = pmap_md_pool_phystov(pa);
@@ -726,10 +743,14 @@ pmap_md_map_poolpage(paddr_t pa, size_t 
 		vaddr_t last_va = trunc_page(pv->pv_va);
 
 		KASSERT(len == PAGE_SIZE || last_va == pa);
+		UVMHIST_LOG(pmaphist, "(last_va=%#lx va=%#lx pa=%#lx)", last_va, va, pa, 0);
+
 		KASSERT(pv->pv_pmap == NULL);
 		KASSERT(pv->pv_next == NULL);
 		KASSERT(!VM_PAGEMD_EXECPAGE_P(mdpg));
 
+		/* XXX What about dirty cache lines and overwriting pool data */
+
 		/*
 		 * If this page was last mapped with an address that
 		 * might cause aliases, flush the page from the cache.
@@ -747,6 +768,8 @@ pmap_md_map_poolpage(paddr_t pa, size_t 
 paddr_t
 pmap_md_unmap_poolpage(vaddr_t va, size_t len)
 {
+	UVMHIST_FUNC(__func__); UVMHIST_CALLED(pmaphist);
+
 	KASSERT(len == PAGE_SIZE);
 	KASSERT(pmap_md_direct_mapped_vaddr_p(va));
 
@@ -767,6 +790,8 @@ pmap_md_unmap_poolpage(vaddr_t va, size_
 	KASSERT(pv->pv_pmap == NULL);
 	KASSERT(pv->pv_next == NULL);
 
+	UVMHIST_LOG(pmaphist, "(va=%#lx pa=%#lx)", va, pa, 0, 0);
+
 	return pa;
 }
 
@@ -934,6 +959,8 @@ pmap_md_vca_add(struct vm_page *pg, vadd
 	 * incompatible with the new mapping then they all will be.
 	 */
 	if (__predict_true(!mips_cache_badalias(pv->pv_va, va))) {
+		UVMHIST_LOG(pmaphist, " no alias pv_va %"PRIxVADDR " vs %"
+		    PRIxVADDR, pv->pv_va, va, 0, 0);
 		return false;
 	}
 	KASSERT(pv->pv_pmap != NULL);
@@ -986,6 +1013,7 @@ pmap_md_vca_add(struct vm_page *pg, vadd
 		*ptep = pte_cached_change(*ptep, false);
 		PMAP_COUNT(page_cache_evictions);
 	}
+	UVMHIST_LOG(pmaphist, " ... done (uncache)", 0, 0, 0, 0);
 	return false;
 #endif	/* !PMAP_NO_PV_UNCACHED */
 }
@@ -1066,3 +1094,21 @@ pmap_md_pool_phystov(paddr_t pa)
 	return MIPS_PHYS_TO_KSEG0(pa);
 #endif
 }
+
+
+void pmap_md_activate(struct lwp *);
+void
+pmap_md_activate(struct lwp *l)
+{
+	UVMHIST_FUNC(__func__); UVMHIST_CALLED(pmaphist);
+
+#ifdef UVMHIST
+	const struct trapframe *tf = l->l_md.md_utf;
+#endif
+	UVMHIST_LOG(pmaphist, "(registers)", 0, 0, 0, 0);
+        for (size_t i = 0; i < 32; i += 2) {
+		UVMHIST_LOG(pmaphist, "  [%2zu]=%08"PRIxREGISTER" [%2zu]=%08"PRIxREGISTER,
+		    i+0, tf->tf_regs[i+0], i+1, tf->tf_regs[i+1]);
+        }
+
+}
Index: sys/arch/mips/mips/spl.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/spl.S,v
retrieving revision 1.17
diff -u -p -w -b -r1.17 spl.S
--- sys/arch/mips/mips/spl.S	12 Apr 2019 21:12:21 -0000	1.17
+++ sys/arch/mips/mips/spl.S	8 Mar 2020 20:36:16 -0000
@@ -42,6 +42,17 @@ RCSID("$NetBSD: spl.S,v 1.17 2019/04/12 
 
 #include "assym.h"
 
+#if (MIPS3 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) != 1
+# error  Only one of MIPS{3,32,32R2,64,64R2} can be defined
+#endif
+
+#if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
+#define MIPSNN
+#if (MIPS32R2 + MIPS64R2) > 0
+#define MIPSNNR2
+#endif
+#endif
+
 	.data
 	.globl	_C_LABEL(ipl_sr_map)
 	.type	_C_LABEL(ipl_sr_map),@object
@@ -80,6 +91,10 @@ _splraise:
 	or	v1, MIPS_INT_MASK		# enable all interrupts
 	xor	a0, v1				# disable ipl's masked bits
 	DYNAMIC_STATUS_MASK(a0,v0)		# machine dependent masking
+
+#if defined(MIPSNNR2)
+	di
+#else
 #if !defined(__mips_o32)
 	or	v1, MIPS_SR_INT_IE		#
 	xor	v1, MIPS_SR_INT_IE		# clear interrupt enable bit
@@ -87,7 +102,9 @@ _splraise:
 #else
 	mtc0	zero, MIPS_COP_0_STATUS		## disable interrupts
 #endif
+#endif
 	COP0_SYNC
+
 #ifdef MULTIPROCESSOR
 	PTR_L	a3, L_CPU(MIPS_CURLWP)		## make sure curcpu is correct
 	NOP_L					## load delay
@@ -137,6 +154,10 @@ STATIC_XLEAF(_splsw_splx_noprof)		# does
 	xor	a1, MIPS_INT_MASK		# invert SR bits
 	or	v1, a1				# set any bits for this IPL
 	DYNAMIC_STATUS_MASK(v1,t0)		# machine dependent masking
+
+#if defined(MIPSNNR2)
+	di
+#else
 #if !defined(__mips_o32)
 	or	v0, v1, MIPS_SR_INT_IE		#
 	xor	v0, MIPS_SR_INT_IE		# clear interrupt enable bit
@@ -144,7 +165,9 @@ STATIC_XLEAF(_splsw_splx_noprof)		# does
 #else
 	mtc0	zero, MIPS_COP_0_STATUS		## disable interrupts
 #endif
+#endif
 	COP0_SYNC
+
 	INT_S	a0, CPU_INFO_CPL(a3)		## save IPL in cpu_info (KSEG0)
 	mtc0	v1, MIPS_COP_0_STATUS		## store back
 	COP0_SYNC
@@ -178,6 +201,10 @@ STATIC_LEAF(_splsw_spl0)
 	MFC0_HAZARD				# load delay
 	or	v0, a0, v1
 	DYNAMIC_STATUS_MASK(v0,t0)		# machine dependent masking
+
+#if defined(MIPSNNR2)
+	di
+#else
 #if !defined(__mips_o32)
 	or	v1, v0, MIPS_SR_INT_IE		#
 	xor	v1, MIPS_SR_INT_IE		# clear interrupt enable bit
@@ -185,6 +212,7 @@ STATIC_LEAF(_splsw_spl0)
 #else
 	mtc0	zero, MIPS_COP_0_STATUS		## disable interrupts
 #endif
+#endif
 	COP0_SYNC
 #if IPL_NONE == 0
 	INT_S	zero, CPU_INFO_CPL(a3)		## set ipl to 0
@@ -196,6 +224,9 @@ STATIC_LEAF(_splsw_spl0)
 END(_splsw_spl0)
 
 STATIC_LEAF(_splsw_setsoftintr)
+#if defined(MIPSNNR2)
+	di
+#else
 	mfc0	v1, MIPS_COP_0_STATUS		# save status register
 #if !defined(__mips_o32)
 	MFC0_HAZARD				# load delay
@@ -205,17 +236,25 @@ STATIC_LEAF(_splsw_setsoftintr)
 #else
 	mtc0	zero, MIPS_COP_0_STATUS		## disable interrupts
 #endif
+#endif
 	COP0_SYNC
 	mfc0	v0, MIPS_COP_0_CAUSE		# fetch cause register
 	MFC0_HAZARD				# load delay
 	or	v0, v0, a0			# set soft intr. bits
 	mtc0	v0, MIPS_COP_0_CAUSE		# store back
 	COP0_SYNC
+#if defined(MIPSNNR2)
+	ei
+#else
 	mtc0	v1, MIPS_COP_0_STATUS		# enable interrupts
+#endif
 	JR_HB_RA				# return (clear hazards)
 END(_splsw_setsoftintr)
 
 STATIC_LEAF(_splsw_clrsoftintr)
+#if defined(MIPSNNR2)
+	di
+#else
 	mfc0	v1, MIPS_COP_0_STATUS		# save status register
 #if !defined(__mips_o32)
 	MFC0_HAZARD				# load delay
@@ -225,13 +264,18 @@ STATIC_LEAF(_splsw_clrsoftintr)
 #else
 	mtc0	zero, MIPS_COP_0_STATUS		## disable interrupts
 #endif
+#endif
 	COP0_SYNC
 	mfc0	v0, MIPS_COP_0_CAUSE		# fetch cause register
 	nor	a0, zero, a0			# bitwise inverse of A0
 	and	v0, v0, a0			# clear soft intr. bits
 	mtc0	v0, MIPS_COP_0_CAUSE		# store back
 	COP0_SYNC
+#if defined(MIPSNNR2)
+	ei
+#else
 	mtc0	v1, MIPS_COP_0_STATUS		# enable interrupts
+#endif
 	JR_HB_RA				# return (clear hazards)
 END(_splsw_clrsoftintr)
 
Index: sys/arch/mips/mips/trap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/trap.c,v
retrieving revision 1.250
diff -u -p -w -b -r1.250 trap.c
--- sys/arch/mips/mips/trap.c	7 Mar 2020 18:49:49 -0000	1.250
+++ sys/arch/mips/mips/trap.c	8 Mar 2020 20:36:16 -0000
@@ -43,6 +43,7 @@ __KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.2
 
 #include "opt_cputype.h"	/* which mips CPU levels do we support? */
 #include "opt_ddb.h"
+#include "opt_kernhist.h"
 #include "opt_kgdb.h"
 #include "opt_multiprocessor.h"
 
@@ -58,6 +59,9 @@ __KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.2
 #include <sys/ktrace.h>
 #include <sys/kauth.h>
 #include <sys/atomic.h>
+#ifdef KERNHIST
+#include <sys/kernhist.h>
+#endif
 
 #include <mips/cache.h>
 #include <mips/locore.h>
@@ -162,6 +166,10 @@ trap(uint32_t status, uint32_t cause, va
 	void *onfault;
 	int rv;
 
+	UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
+	UVMHIST_LOG(maphist, "status %08x cause %08x va %"PRIxVADDR
+	    " pc %"PRIxVADDR, status, cause, vaddr, pc);
+
 	KSI_INIT_TRAP(&ksi);
 
 	curcpu()->ci_data.cpu_ntrap++;
@@ -176,6 +184,13 @@ trap(uint32_t status, uint32_t cause, va
 		LWP_CACHE_CREDS(l, p);
 	}
 
+	UVMHIST_LOG(maphist, "... tf %p", tf, 0, 0, 0);
+        for (size_t i = 0; i < 32; i += 2) {
+		UVMHIST_LOG(pmaphist,
+		    "  [%2zu]=%08"PRIxREGISTER" [%2zu]=%08"PRIxREGISTER,
+		    i+0, tf->tf_regs[i+0], i+1, tf->tf_regs[i+1]);
+	}
+
 	switch (type) {
 	default:
 	dopanic:
@@ -278,7 +293,6 @@ trap(uint32_t status, uint32_t cause, va
 				goto kernelfault;
 			}
 		}
-		UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
 		UVMHIST_LOG(maphist, "%ctlbmod(va=%#lx, pc=%#lx, tf=%p)",
 		    user_p ? 'u' : 'k', vaddr, pc, tf);
 		if (!pte_modified_p(pte)) {
@@ -624,6 +638,9 @@ trap(uint32_t status, uint32_t cause, va
 		    i+0, utf->tf_regs[i+0], i+1, utf->tf_regs[i+1],
 		    i+2, utf->tf_regs[i+2], i+3, utf->tf_regs[i+3]);
 	}
+#ifdef DDB
+		Debugger();
+#endif
 #endif
 	(*p->p_emul->e_trapsignal)(l, &ksi);
 	if ((type & T_USER) == 0) {
Index: sys/ddb/db_output.c
===================================================================
RCS file: /cvsroot/src/sys/ddb/db_output.c,v
retrieving revision 1.36
diff -u -p -w -b -r1.36 db_output.c
--- sys/ddb/db_output.c	26 Jan 2020 01:42:55 -0000	1.36
+++ sys/ddb/db_output.c	8 Mar 2020 20:36:17 -0000
@@ -62,7 +62,7 @@ __KERNEL_RCSID(0, "$NetBSD: db_output.c,
 #define	DB_MAX_LINE		24	/* maximum line */
 #endif	/* DB_MAX_LINE */
 #ifndef	DB_MAX_WIDTH
-#define DB_MAX_WIDTH		80	/* maximum width */
+#define DB_MAX_WIDTH		0	/* maximum width */
 #endif	/* DB_MAX_WIDTH */
 
 #define DB_MIN_MAX_WIDTH	20	/* minimum max width */
Index: sys/uvm/uvm_map.c
===================================================================
RCS file: /cvsroot/src/sys/uvm/uvm_map.c,v
retrieving revision 1.372
diff -u -p -w -b -r1.372 uvm_map.c
--- sys/uvm/uvm_map.c	23 Feb 2020 15:46:43 -0000	1.372
+++ sys/uvm/uvm_map.c	8 Mar 2020 20:36:19 -0000
@@ -2278,6 +2278,7 @@ uvm_unmap_remove(struct vm_map *map, vad
 		next = entry->next;
 		len = entry->end - entry->start;
 
+		UVMHIST_LOG(maphist, "  map entry %p [%#"PRIxVADDR "..%#"PRIxVADDR, entry, entry->start, entry->end, 0);
 		/*
 		 * unwire before removing addresses from the pmap; otherwise
 		 * unwiring will put the entries back into the pmap (XXX).
@@ -2321,8 +2322,10 @@ uvm_unmap_remove(struct vm_map *map, vad
 			 */
 
 			if ((map->flags & VM_MAP_DYING) == 0) {
+				UVMHIST_LOG(maphist," not dying... pmap_update", 0, 0, 0, 0);
 				pmap_update(vm_map_pmap(map));
 			} else {
+				UVMHIST_LOG(maphist," dying...", 0, 0, 0, 0);
 				KASSERT(vm_map_pmap(map) != pmap_kernel());
 			}
 
@@ -2378,14 +2381,16 @@ uvm_unmap_remove(struct vm_map *map, vad
 	 */
 
 	*entry_list = first_entry;
-	UVMHIST_LOG(maphist,"<- done!", 0, 0, 0, 0);
 
 	if (map->flags & VM_MAP_WANTVA) {
+		UVMHIST_LOG(maphist," want va", 0, 0, 0, 0);
 		mutex_enter(&map->misc_lock);
 		map->flags &= ~VM_MAP_WANTVA;
 		cv_broadcast(&map->cv);
 		mutex_exit(&map->misc_lock);
+		UVMHIST_LOG(maphist," want va done", 0, 0, 0, 0);
 	}
+	UVMHIST_LOG(maphist,"<- done!", 0, 0, 0, 0);
 }
 
 /*
@@ -4177,6 +4182,8 @@ uvmspace_exec(struct lwp *l, vaddr_t sta
 	struct vmspace *nvm, *ovm = p->p_vmspace;
 	struct vm_map *map;
 
+	UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
+
 	KASSERT(ovm != NULL);
 #ifdef __HAVE_CPU_VMSPACE_EXEC
 	cpu_vmspace_exec(l, start, end);
@@ -4190,6 +4197,7 @@ uvmspace_exec(struct lwp *l, vaddr_t sta
 	if (ovm->vm_refcnt == 1
 	    && topdown == ((ovm->vm_map.flags & VM_MAP_TOPDOWN) != 0)) {
 
+		UVMHIST_LOG(maphist,"(vm=%p) ref=%d", ovm, ovm->vm_refcnt,0,0);
 		/*
 		 * if p is the only process using its vmspace then we can safely
 		 * recycle that vmspace for the program that is being exec'd.
@@ -4235,6 +4243,8 @@ uvmspace_exec(struct lwp *l, vaddr_t sta
 
 		nvm = uvmspace_alloc(start, end, topdown);
 
+		UVMHIST_LOG(maphist,"(ovm=%p nvm=%p)", ovm, nvm, 0, 0);
+
 		/*
 		 * install new vmspace and drop our ref to the old one.
 		 */
@@ -4300,11 +4310,15 @@ uvmspace_free(struct vmspace *vm)
 	KASSERT(map->nentries == 0);
 	KASSERT(map->size == 0);
 
+	UVMHIST_LOG(maphist," all gone",0,0,0,0);
+
 	mutex_destroy(&map->misc_lock);
 	rw_destroy(&map->lock);
 	cv_destroy(&map->cv);
 	pmap_destroy(map->pmap);
 	pool_cache_put(&uvm_vmspace_cache, vm);
+
+	UVMHIST_LOG(maphist,"<- done",0,0,0,0);
 }
 
 static struct vm_map_entry *
Index: sys/uvm/pmap/pmap.c
===================================================================
RCS file: /cvsroot/src/sys/uvm/pmap/pmap.c,v
retrieving revision 1.45
diff -u -p -w -b -r1.45 pmap.c
--- sys/uvm/pmap/pmap.c	18 Dec 2019 10:55:50 -0000	1.45
+++ sys/uvm/pmap/pmap.c	8 Mar 2020 20:36:19 -0000
@@ -183,6 +183,7 @@ PMAP_COUNTER(copy, "copies");
 PMAP_COUNTER(clear_modify, "clear_modifies");
 PMAP_COUNTER(protect, "protects");
 PMAP_COUNTER(page_protect, "page_protects");
+PMAP_COUNTER(remove_skipped, "page_remove skipped PVs");
 
 #define PMAP_ASID_RESERVED 0
 CTASSERT(PMAP_ASID_RESERVED == 0);
@@ -214,12 +215,14 @@ struct pmap_limits pmap_limits = {	/* VA
 	.virtual_start = VM_MIN_KERNEL_ADDRESS,
 };
 
+#if 0
 #ifdef UVMHIST
 static struct kern_history_ent pmapexechistbuf[10000];
 static struct kern_history_ent pmaphistbuf[10000];
 UVMHIST_DEFINE(pmapexechist);
 UVMHIST_DEFINE(pmaphist);
 #endif
+#endif
 
 /*
  * The pools from which pmap structures and sub-structures are allocated.
@@ -529,8 +532,10 @@ pmap_steal_memory(vsize_t size, vaddr_t 
 void
 pmap_init(void)
 {
+#if 0
 	UVMHIST_INIT_STATIC(pmapexechist, pmapexechistbuf);
 	UVMHIST_INIT_STATIC(pmaphist, pmaphistbuf);
+#endif
 
 	UVMHIST_FUNC(__func__); UVMHIST_CALLED(pmaphist);
 
@@ -581,6 +586,7 @@ pmap_create(void)
 	memset(pmap, 0, PMAP_SIZE);
 
 	KASSERT(pmap->pm_pai[0].pai_link.le_prev == NULL);
+	KASSERT(pmap->pm_flags == 0);
 
 	pmap->pm_count = 1;
 	pmap->pm_minaddr = VM_MIN_ADDRESS;
@@ -606,6 +612,7 @@ pmap_create(void)
  *	Should only be called if the map contains
  *	no valid mappings.
  */
+int nhdebug;
 void
 pmap_destroy(pmap_t pmap)
 {
@@ -656,6 +663,8 @@ pmap_reference(pmap_t pmap)
 	UVMHIST_LOG(pmaphist, " <-- done", 0, 0, 0, 0);
 }
 
+void pmap_md_activate(struct lwp *);
+
 /*
  *	Make a new pmap (vmspace) active for the given process.
  */
@@ -676,6 +685,9 @@ pmap_activate(struct lwp *l)
 		pmap_segtab_activate(pmap, l);
 	}
 	pmap_md_tlb_miss_lock_exit();
+
+	pmap_md_activate(l);
+
 	kpreempt_enable();
 
 	UVMHIST_LOG(pmaphist, " <-- done (%ju:%ju)", l->l_proc->p_pid,
@@ -757,11 +769,17 @@ pmap_page_remove(struct vm_page *pg)
 		KASSERTMSG(ptep != NULL, "%#"PRIxVADDR " %#"PRIxVADDR, va,
 		    pmap_limits.virtual_end);
 		pt_entry_t pte = *ptep;
+
 		UVMHIST_LOG(pmaphist, " pv %#jx pmap %#jx va %jx"
 		    " pte %jx", (uintptr_t)pv, (uintptr_t)pmap, va,
 		    pte_value(pte));
-		if (!pte_valid_p(pte))
+
+		/* XXX do we care??? - all non-PV_KENTRIES entries need to go */
+		if (!pte_valid_p(pte)) {
+			PMAP_COUNT(remove_skipped);
+			UVMHIST_LOG(pmaphist, " ... skip", 0, 0, 0, 0);
 			continue;
+		}
 		const bool is_kernel_pmap_p = (pmap == pmap_kernel());
 		if (is_kernel_pmap_p) {
 			PMAP_COUNT(remove_kernel_pages);
@@ -795,6 +813,17 @@ pmap_page_remove(struct vm_page *pg)
 			pv->pv_pmap = NULL;
 			pv->pv_next = NULL;
 		}
+		UVMHIST_LOG(pmaphist, " ... deleted", 0, 0, 0, 0);
+
+	}
+
+	pv_entry_t xpv = &mdpg->mdpg_first;
+	if (xpv->pv_pmap != NULL) {
+		for (; xpv != NULL; xpv = xpv->pv_next) {
+			KASSERT(xpv->pv_va & PV_KENTER);
+		}
+	} else {
+	    	KASSERT(xpv->pv_next == NULL);
 	}
 
 	pmap_pvlist_check(mdpg);
@@ -804,7 +833,6 @@ pmap_page_remove(struct vm_page *pg)
 	UVMHIST_LOG(pmaphist, " <-- done", 0, 0, 0, 0);
 }
 
-
 /*
  *	Make a previously active pmap (vmspace) inactive.
  */
@@ -814,8 +842,8 @@ pmap_deactivate(struct lwp *l)
 	pmap_t pmap = l->l_proc->p_vmspace->vm_map.pmap;
 
 	UVMHIST_FUNC(__func__); UVMHIST_CALLED(pmaphist);
-	UVMHIST_LOG(pmaphist, "(l=%#jx pmap=%#jx)", (uintptr_t)l,
-	    (uintptr_t)pmap, 0, 0);
+	UVMHIST_LOG(pmaphist, "(l=%#jx pmap=%#jx from %#jx)", (uintptr_t)l,
+	    (uintptr_t)pmap, (uintptr_t)__builtin_return_address(0), 0);
 	PMAP_COUNT(deactivate);
 
 	kpreempt_disable();
@@ -837,7 +865,8 @@ void
 pmap_update(struct pmap *pmap)
 {
 	UVMHIST_FUNC(__func__); UVMHIST_CALLED(pmaphist);
-	UVMHIST_LOG(pmaphist, "(pmap=%#jx)", (uintptr_t)pmap, 0, 0, 0);
+	UVMHIST_LOG(pmaphist, "(pmap=%#jx)", (uintptr_t)pmap,
+	    !!(pmap->pm_flags & PMAP_DEFERRED_ACTIVATE), 0, 0);
 	PMAP_COUNT(update);
 
 	kpreempt_disable();
@@ -1747,6 +1776,7 @@ pmap_pvlist_check(struct vm_page_md *mdp
 	} else {
     		KASSERT(pv->pv_next == NULL);
 	}
+
 #endif /* DEBUG */
 }
 
@@ -1795,6 +1825,7 @@ again:
 		KASSERT(VM_PAGEMD_CACHED_P(mdpg));
 		// If the new mapping has an incompatible color the last
 		// mapping of this page, clean the page before using it.
+		// XXX Invalidate?!?
 		if (!PMAP_PAGE_COLOROK_P(va, pv->pv_va)) {
 			pmap_md_vca_clean(pg, PMAP_WBINV);
 		}
@@ -1938,6 +1969,7 @@ pmap_remove_pv(pmap_t pmap, vaddr_t va, 
 			pmap_page_clear_attributes(mdpg, VM_PAGEMD_UNCACHED);
 #endif
 			pv->pv_pmap = NULL;
+			pv->pv_next = NULL;	/* XXX do we need to sprinkle this ??? */
 			last = true;	/* Last mapping removed */
 		}
 		PMAP_COUNT(remove_pvfirst);
@@ -2155,6 +2187,7 @@ pmap_map_poolpage(paddr_t pa)
 	KASSERT(!VM_PAGEMD_EXECPAGE_P(mdpg));
 
 	pmap_page_set_attributes(mdpg, VM_PAGEMD_POOLPAGE);
+	KASSERT(!VM_PAGEMD_EXECPAGE_P(mdpg));
 
 	return pmap_md_map_poolpage(pa, NBPG);
 }
@@ -2170,6 +2203,7 @@ pmap_unmap_poolpage(vaddr_t va)
 	KASSERT(!VM_PAGEMD_EXECPAGE_P(VM_PAGE_TO_MD(pg)));
 
 	pmap_page_clear_attributes(VM_PAGE_TO_MD(pg), VM_PAGEMD_POOLPAGE);
+	KASSERT(!VM_PAGEMD_EXECPAGE_P(VM_PAGE_TO_MD(pg)));
 	pmap_md_unmap_poolpage(va, NBPG);
 
 	return pa;
Index: sys/uvm/pmap/pmap.h
===================================================================
RCS file: /cvsroot/src/sys/uvm/pmap/pmap.h,v
retrieving revision 1.12
diff -u -p -w -b -r1.12 pmap.h
--- sys/uvm/pmap/pmap.h	1 Jun 2019 12:42:28 -0000	1.12
+++ sys/uvm/pmap/pmap.h	8 Mar 2020 20:36:19 -0000
@@ -75,10 +75,15 @@
 #define	_UVM_PMAP_PMAP_H_
 
 #include <uvm/uvm_stat.h>
+#if 0
 #ifdef UVMHIST
 UVMHIST_DECL(pmapexechist);
 UVMHIST_DECL(pmaphist);
 #endif
+#endif
+UVMHIST_DECL(maphist);
+#define pmaphist maphist
+#define pmapexechist maphist
 
 /*
  * The user address space is mapped using a two level structure where
Index: sys/uvm/pmap/pmap_tlb.c
===================================================================
RCS file: /cvsroot/src/sys/uvm/pmap/pmap_tlb.c,v
retrieving revision 1.30
diff -u -p -w -b -r1.30 pmap_tlb.c
--- sys/uvm/pmap/pmap_tlb.c	18 Dec 2019 11:27:56 -0000	1.30
+++ sys/uvm/pmap/pmap_tlb.c	8 Mar 2020 20:36:19 -0000
@@ -213,6 +213,8 @@ pmap_tlb_intersecting_onproc_p(pmap_t pm
 static void
 pmap_tlb_pai_check(struct pmap_tlb_info *ti, bool locked_p)
 {
+    	UVMHIST_FUNC(__func__); UVMHIST_CALLED(pmaphist);
+
 #ifdef DIAGNOSTIC
 	struct pmap_asid_info *pai;
 	if (!locked_p)
@@ -232,6 +234,7 @@ pmap_tlb_pai_check(struct pmap_tlb_info 
 	if (!locked_p)
 		TLBINFO_UNLOCK(ti);
 #endif
+	UVMHIST_LOG(pmaphist, " <-- done", 0, 0, 0, 0);
 }
 
 static void
@@ -267,9 +270,13 @@ pmap_tlb_pai_reset(struct pmap_tlb_info 
 	 */
 	if (PMAP_TLB_FLUSH_ASID_ON_RESET) {
 #ifndef MULTIPROCESSOR
+		UVMHIST_LOG(maphist, " ... asid %u flushed", pai->pai_asid, 0,
+		    0, 0);
 		tlb_invalidate_asids(pai->pai_asid, pai->pai_asid);
 #endif
 		if (TLBINFO_ASID_INUSE_P(ti, pai->pai_asid)) {
+			UVMHIST_LOG(maphist, " ... asid marked unused",
+			    pai->pai_asid, 0, 0, 0);
 			TLBINFO_ASID_MARK_UNUSED(ti, pai->pai_asid);
 			ti->ti_asids_free++;
 		}
@@ -362,13 +369,13 @@ pmap_tlb_info_init(struct pmap_tlb_info 
 #endif /* MULTIPROCESSOR */
 	KASSERT(ti == &pmap_tlb0_info);
 	KASSERT(ti->ti_lock == &pmap_tlb0_lock);
-	//printf("ti_lock %p ", ti->ti_lock);
+
 	mutex_init(ti->ti_lock, MUTEX_DEFAULT, IPL_SCHED);
 #if defined(MULTIPROCESSOR) && PMAP_TLB_MAX > 1
 	kcpuset_create(&ti->ti_kcpuset, true);
 	kcpuset_set(ti->ti_kcpuset, cpu_index(curcpu()));
 #endif
-	//printf("asid ");
+
 	if (ti->ti_asid_max == 0) {
 		ti->ti_asid_max = pmap_md_tlb_asid_max();
 		ti->ti_asids_free = TLBINFO_ASID_INITIAL_FREE(ti->ti_asid_max);
@@ -992,10 +999,16 @@ pmap_tlb_asid_deactivate(pmap_t pm)
 	curcpu()->ci_pmap_asid_cur = KERNEL_PID;
 	UVMHIST_LOG(maphist, " <-- done (pm=%#jx)", (uintptr_t)pm, 0, 0, 0);
 	tlb_set_asid(KERNEL_PID);
+	UVMHIST_LOG(maphist, " set %u", KERNEL_PID, 0, 0, 0);
+	//is TI valid here ???
+	UVMHIST_LOG(maphist, " ti %p", cpu_tlb_info(curcpu()), 0, 0, 0);
+
 	pmap_tlb_pai_check(cpu_tlb_info(curcpu()), false);
+	UVMHIST_LOG(maphist, " pmap_tlb_pai_check", 0, 0, 0, 0);
 #if defined(DEBUG)
 	pmap_tlb_asid_check();
 #endif
+	UVMHIST_LOG(maphist, " <-- done (pm=%p)", pm, 0, 0, 0);
 }
 
 void
@@ -1062,14 +1075,18 @@ pmap_tlb_asid_release_all(struct pmap *p
 void
 pmap_tlb_asid_check(void)
 {
+    	UVMHIST_FUNC(__func__); UVMHIST_CALLED(pmaphist);
+
 #ifdef DEBUG
 	kpreempt_disable();
 	const tlb_asid_t asid __debugused = tlb_get_asid();
+	UVMHIST_LOG(pmaphist, " asid %u vs pmap_curasid %u", asid, curcpu()->ci_pmap_asid_cur, 0, 0);
 	KDASSERTMSG(asid == curcpu()->ci_pmap_asid_cur,
 	   "%s: asid (%#x) != current asid (%#x)",
 	    __func__, asid, curcpu()->ci_pmap_asid_cur);
 	kpreempt_enable();
 #endif
+	UVMHIST_LOG(pmaphist, " <-- done", 0, 0, 0, 0);
 }
 
 #ifdef DEBUG