ffffc00000004460 <gic_splx>:

static void __noasan
gic_splx(int newipl)
{
ffffc00000004460:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
	__asm("mrs %0, tpidr_el1" : "=r"(l));
ffffc00000004464:	d538d081 	mrs	x1, tpidr_el1
ffffc00000004468:	910003fd 	mov	x29, sp
ffffc0000000446c:	a90153f3 	stp	x19, x20, [sp, #16]
ffffc00000004470:	f9400033 	ldr	x19, [x1]
ffffc00000004474:	2a0003e1 	mov	w1, w0
	struct cpu_info *ci = curcpu();
	register_t psw;

	if (newipl >= ci->ci_cpl) {
ffffc00000004478:	b9453260 	ldr	w0, [x19, #1328]
ffffc0000000447c:	6b01001f 	cmp	w0, w1
ffffc00000004480:	5400044d 	b.le	ffffc00000004508 <gic_splx+0xa8>
	 *
	 * If an interrupt fires in this critical section, the vector
	 * handler is responsible for returning to the address pointed
	 * to by ci_splx_restart to restart the sequence.
	 */
	if (__predict_true(ci->ci_intr_depth == 0)) {
ffffc00000004484:	b9453e60 	ldr	w0, [x19, #1340]
ffffc00000004488:	35000100 	cbnz	w0, ffffc000000044a8 <gic_splx+0x48>
		ci->ci_splx_restart = &&restart;
ffffc0000000448c:	90000000 	adrp	x0, ffffc00000004000 <pic_default_splraise+0x70>
ffffc00000004490:	91123000 	add	x0, x0, #0x48c						; XXXNH x0 = ffffc0000000448c!
ffffc00000004494:	f902aa60 	str	x0, [x19, #1360]


		__insn_barrier();
restart:
		if (ci->ci_hwpl <= newipl) {
ffffc00000004498:	b9453660 	ldr	w0, [x19, #1332]
ffffc0000000449c:	6b01001f 	cmp	w0, w1
ffffc000000044a0:	540003ad 	b.le	ffffc00000004514 <gic_splx+0xb4>
		}
		/*
		 * An interrupt fired and raised ci->ci_hwpl above newipl
		 * which means we can (and should) call the handler.
		 */
		ci->ci_splx_restart = NULL;
ffffc000000044a4:	f902aa7f 	str	xzr, [x19, #1360]
AARCH64REG_READ_INLINE(daif)		// Debug Async Irq Fiq mask register
ffffc000000044a8:	d53b4234 	mrs	x20, daif
ffffc000000044ac:	927a0680 	and	x0, x20, #0xc0
ffffc000000044b0:	f103001f 	cmp	x0, #0xc0
ffffc000000044b4:	54000040 	b.eq	ffffc000000044bc <gic_splx+0x5c>  // b.none
AARCH64REG_WRITEIMM_INLINE(daifset)
ffffc000000044b8:	d50343df 	msr	daifset, #0x3
	}

	psw = DISABLE_INTERRUPT_SAVE();
	ci->ci_intr_depth++;
ffffc000000044bc:	b9453e63 	ldr	w3, [x19, #1340]
	pic_do_pending_ints(psw, newipl, NULL);
ffffc000000044c0:	aa1403e0 	mov	x0, x20
ffffc000000044c4:	d2800002 	mov	x2, #0x0                   	// #0
	ci->ci_intr_depth++;
ffffc000000044c8:	11000463 	add	w3, w3, #0x1
ffffc000000044cc:	b9053e63 	str	w3, [x19, #1340]
	pic_do_pending_ints(psw, newipl, NULL);
ffffc000000044d0:	97fff950 	bl	ffffc00000002a10 <pic_do_pending_ints>
	ci->ci_intr_depth--;
ffffc000000044d4:	b9453e60 	ldr	w0, [x19, #1340]
ffffc000000044d8:	51000400 	sub	w0, w0, #0x1
ffffc000000044dc:	b9053e60 	str	w0, [x19, #1340]
	if ((psw & I32_bit) == 0) {
ffffc000000044e0:	37380054 	tbnz	w20, #7, ffffc000000044e8 <gic_splx+0x88>
AARCH64REG_WRITEIMM_INLINE(daifclr)
ffffc000000044e4:	d50343ff 	msr	daifclr, #0x3
ffffc000000044e8:	d538d080 	mrs	x0, tpidr_el1
ffffc000000044ec:	f9400000 	ldr	x0, [x0]
	if (ci->ci_intr_depth == 0 && (ci->ci_softints >> ci->ci_cpl) > 0) {
ffffc000000044f0:	b9453c01 	ldr	w1, [x0, #1340]
ffffc000000044f4:	350000a1 	cbnz	w1, ffffc00000004508 <gic_splx+0xa8>
ffffc000000044f8:	b9453801 	ldr	w1, [x0, #1336]
ffffc000000044fc:	b9453000 	ldr	w0, [x0, #1328]
ffffc00000004500:	1ac02420 	lsr	w0, w1, w0
ffffc00000004504:	350000e0 	cbnz	w0, ffffc00000004520 <gic_splx+0xc0>
		ENABLE_INTERRUPT();
	}

dosoft:
	cpu_dosoftints();
}
ffffc00000004508:	a94153f3 	ldp	x19, x20, [sp, #16]
ffffc0000000450c:	a8c27bfd 	ldp	x29, x30, [sp], #32
ffffc00000004510:	d65f03c0 	ret
			ci->ci_cpl = newipl;
ffffc00000004514:	b9053261 	str	w1, [x19, #1328]
			ci->ci_splx_restart = NULL;
ffffc00000004518:	f902aa7f 	str	xzr, [x19, #1360]
			goto dosoft;
ffffc0000000451c:	17fffff3 	b	ffffc000000044e8 <gic_splx+0x88>
}
ffffc00000004520:	a94153f3 	ldp	x19, x20, [sp, #16]
ffffc00000004524:	a8c27bfd 	ldp	x29, x30, [sp], #32
		dosoftints();
ffffc00000004528:	14029182 	b	ffffc000000a8b30 <dosoftints>
ffffc0000000452c:	d503201f 	nop