? sys/cscope.out
Index: sys/arch/algor/algor/algor_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/algor/algor/algor_intr.c,v
retrieving revision 1.1
diff -u -p -r1.1 algor_intr.c
--- sys/arch/algor/algor/algor_intr.c	9 Jul 2011 16:03:00 -0000	1.1
+++ sys/arch/algor/algor/algor_intr.c	26 Aug 2016 13:44:59 -0000
@@ -102,7 +102,7 @@ intr_init(void)
 
 #ifdef evbmips
 void
-evbmips_iointr(int ipl, vaddr_t pc, uint32_t pending)
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t pending, uint32_t status)
 {
 	(*algor_iointr)(ipl, pc, pending);
 }
Index: sys/arch/evbmips/alchemy/mach_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/alchemy/mach_intr.c,v
retrieving revision 1.6
diff -u -p -r1.6 mach_intr.c
--- sys/arch/evbmips/alchemy/mach_intr.c	10 Jul 2011 00:03:52 -0000	1.6
+++ sys/arch/evbmips/alchemy/mach_intr.c	26 Aug 2016 13:45:10 -0000
@@ -61,7 +61,7 @@ evbmips_intr_init(void)
 }
 
 void
-evbmips_iointr(int ipl, uint32_t pc, uint32_t ipending)
+evbmips_iointr(int ipl, uint32_t pc, uint32_t ipending, uint32_t status)
 {
 
 	au_iointr(ipl, pc, ipending);
Index: sys/arch/evbmips/atheros/mach_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/atheros/mach_intr.c,v
retrieving revision 1.6
diff -u -p -r1.6 mach_intr.c
--- sys/arch/evbmips/atheros/mach_intr.c	10 Jul 2011 00:03:53 -0000	1.6
+++ sys/arch/evbmips/atheros/mach_intr.c	26 Aug 2016 13:45:10 -0000
@@ -55,7 +55,7 @@ evbmips_intr_init(void)
 }
 
 void
-evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending, uint32_t status)
 {
 
 	(*platformsw->apsw_intrsw->aisw_iointr)(ipl, pc, ipending);
Index: sys/arch/evbmips/cavium/mach_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/cavium/mach_intr.c,v
retrieving revision 1.2
diff -u -p -r1.2 mach_intr.c
--- sys/arch/evbmips/cavium/mach_intr.c	1 Jun 2015 22:55:12 -0000	1.2
+++ sys/arch/evbmips/cavium/mach_intr.c	26 Aug 2016 13:45:11 -0000
@@ -61,7 +61,7 @@ evbmips_intr_init(void)
 }
 
 void
-evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending, uint32_t status)
 {
 
 	octeon_iointr(ipl, pc, ipending);
Index: sys/arch/evbmips/evbmips/interrupt.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/evbmips/interrupt.c,v
retrieving revision 1.23
diff -u -p -r1.23 interrupt.c
--- sys/arch/evbmips/evbmips/interrupt.c	26 Aug 2016 07:07:29 -0000	1.23
+++ sys/arch/evbmips/evbmips/interrupt.c	26 Aug 2016 13:45:11 -0000
@@ -92,7 +92,7 @@ cpu_intr(int ppl, vaddr_t pc, uint32_t s
 
 		if (pending != 0) {
 			/* Process I/O and error interrupts. */
-			evbmips_iointr(ipl, pc, pending);
+			evbmips_iointr(ipl, pc, pending, status);
 		}
 		KASSERT(biglock_count == ci->ci_biglock_count);
 		KASSERT(blcnt == curlwp->l_blcnt);
Index: sys/arch/evbmips/gdium/gdium_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/gdium/gdium_intr.c,v
retrieving revision 1.7
diff -u -p -r1.7 gdium_intr.c
--- sys/arch/evbmips/gdium/gdium_intr.c	29 Mar 2014 19:28:28 -0000	1.7
+++ sys/arch/evbmips/gdium/gdium_intr.c	26 Aug 2016 13:45:11 -0000
@@ -297,7 +297,7 @@ evbmips_intr_disestablish(void *cookie)
 }
 
 void
-evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending, uint32_t status)
 {
 	struct evbmips_intrhand *ih;
 	int level;
Index: sys/arch/evbmips/include/intr.h
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/include/intr.h,v
retrieving revision 1.19
diff -u -p -r1.19 intr.h
--- sys/arch/evbmips/include/intr.h	9 Jul 2011 16:03:01 -0000	1.19
+++ sys/arch/evbmips/include/intr.h	26 Aug 2016 13:45:11 -0000
@@ -48,7 +48,7 @@ struct evbmips_intrhand {
 
 void	intr_init(void);
 void	evbmips_intr_init(void);
-void	evbmips_iointr(int, vaddr_t, uint32_t);
+void	evbmips_iointr(int, vaddr_t, uint32_t, uint32_t);
 void	*evbmips_intr_establish(int, int (*)(void *), void *);
 void	evbmips_intr_disestablish(void *);
 
Index: sys/arch/evbmips/ingenic/clock.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/ingenic/clock.c,v
retrieving revision 1.7
diff -u -p -r1.7 clock.c
--- sys/arch/evbmips/ingenic/clock.c	29 Jan 2016 01:54:14 -0000	1.7
+++ sys/arch/evbmips/ingenic/clock.c	26 Aug 2016 13:45:11 -0000
@@ -44,7 +44,7 @@ __KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.
 
 extern void ingenic_puts(const char *);
 
-void ingenic_clockintr(uint32_t);
+void ingenic_clockintr(struct clockframe *);
 
 static u_int
 ingenic_count_read(struct timecounter *tc)
@@ -191,9 +191,8 @@ int cnt = 99;
 #endif
 
 void
-ingenic_clockintr(uint32_t id)
+ingenic_clockintr(struct clockframe *cf)
 {
-	extern struct clockframe cf;
 	int s = splsched();
 	struct cpu_info * const ci = curcpu();
 #ifdef USE_OST
@@ -239,6 +238,6 @@ ingenic_clockintr(uint32_t id)
 	 */
 	MTC0(1 << IPI_CLOCK, 20, 1);
 #endif
-	hardclock(&cf);
+	hardclock(cf);
 	splx(s);
 }
Index: sys/arch/evbmips/ingenic/intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/ingenic/intr.c,v
retrieving revision 1.10
diff -u -p -r1.10 intr.c
--- sys/arch/evbmips/ingenic/intr.c	29 Jan 2016 01:54:14 -0000	1.10
+++ sys/arch/evbmips/ingenic/intr.c	26 Aug 2016 13:45:11 -0000
@@ -54,9 +54,8 @@ __KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.1
 #define DPRINTF while (0) printf
 #endif
 
-extern void ingenic_clockintr(uint32_t);
+extern void ingenic_clockintr(struct clockframe *);
 extern void ingenic_puts(const char *);
-extern struct clockframe cf;
 /*
  * This is a mask of bits to clear in the SR when we go to a
  * given hardware interrupt priority level.
@@ -139,7 +138,7 @@ evbmips_intr_init(void)
 }
 
 void
-evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending, uint32_t status)
 {
 	uint32_t id;
 #ifdef INGENIC_INTR_DEBUG
@@ -154,6 +153,13 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 	/* see which core we're on */
 	id = MFC0(15, 1) & 7;
 
+	struct cpu_info * const ci = curcpu();
+	struct clockframe cf;
+
+	cf.pc = pc;
+	cf.sr = status;
+	cf.intr = (ci->ci_idepth > 1);
+
 	/*
 	 * XXX
 	 * the manual counts the softint bits as INT0 and INT1, our headers
@@ -209,7 +215,7 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 	}
 	if (ipending & MIPS_INT_MASK_2) {
 		/* this is a timer interrupt */
-		ingenic_clockintr(id);
+		ingenic_clockintr(&cf);
 		clockintrs.ev_count++;
 		ingenic_puts("INT2\n");
 	}
@@ -230,7 +236,7 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 		mask = readreg(JZ_ICPR0);
 		if (mask & 0x0c000000) {
 			writereg(JZ_ICMSR0, 0x0c000000);
-			ingenic_clockintr(id);
+			ingenic_clockintr(&cf);
 			writereg(JZ_ICMCR0, 0x0c000000);
 			clockintrs.ev_count++;
 		}
Index: sys/arch/evbmips/loongson/loongson_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/loongson/loongson_intr.c,v
retrieving revision 1.4
diff -u -p -r1.4 loongson_intr.c
--- sys/arch/evbmips/loongson/loongson_intr.c	29 Mar 2014 19:28:28 -0000	1.4
+++ sys/arch/evbmips/loongson/loongson_intr.c	26 Aug 2016 13:45:11 -0000
@@ -136,7 +136,7 @@ evbmips_intr_init(void)
 }
 
 void
-evbmips_iointr(int ppl, vaddr_t pc, uint32_t ipending)
+evbmips_iointr(int ppl, vaddr_t pc, uint32_t ipending, uint32_t status)
 {
 	struct evbmips_intrhand *ih;
 	int irq;
@@ -156,13 +156,23 @@ evbmips_iointr(int ppl, vaddr_t pc, uint
 		REGVAL(BONITO_INTENCLR) = isr;
 		(void)REGVAL(BONITO_INTENCLR);
 
+		struct cpu_info * const ci = curcpu();
+		struct clockframe cf;
+
+		cf.pc = pc;
+		cf.sr = status;
+		cf.intr = (ci->ci_idepth > 1);
+
 		for (irq = 0; irq < BONITO_NINTS; irq++) {
 			if ((isr & (1 << irq)) == 0)
 				continue;
 			bonito_intrhead[irq].intr_count.ev_count++;
 			LIST_FOREACH (ih,
 			    &bonito_intrhead[irq].intrhand_head, ih_q) {
-				(*ih->ih_func)(ih->ih_arg);
+				if (ih->ih_arg)
+					(*ih->ih_func)(ih->ih_arg);
+				else
+					(*ih->ih_func)(&cf);
 			}
 		}
 		REGVAL(BONITO_INTENSET) = isr;
Index: sys/arch/evbmips/malta/malta_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/malta/malta_intr.c,v
retrieving revision 1.24
diff -u -p -r1.24 malta_intr.c
--- sys/arch/evbmips/malta/malta_intr.c	31 Mar 2014 20:44:19 -0000	1.24
+++ sys/arch/evbmips/malta/malta_intr.c	26 Aug 2016 13:45:11 -0000
@@ -248,7 +248,7 @@ evbmips_intr_disestablish(void *arg)
 }
 
 void
-evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending, uint32_t status)
 {
 	
 	/* Check for error interrupts (SMI, GT64120) */
Index: sys/arch/mips/adm5120/adm5120_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/adm5120/adm5120_intr.c,v
retrieving revision 1.6
diff -u -p -r1.6 adm5120_intr.c
--- sys/arch/mips/adm5120/adm5120_intr.c	10 Jul 2011 23:13:23 -0000	1.6
+++ sys/arch/mips/adm5120/adm5120_intr.c	26 Aug 2016 13:45:15 -0000
@@ -265,7 +265,7 @@ adm5120_intr_disestablish(void *cookie)
 	free(ih, M_DEVBUF);
 }
 void
-evbmips_iointr(int ipl, uint32_t pc, uint32_t ipending)
+evbmips_iointr(int ipl, uint32_t pc, uint32_t ipending, uint32_t status)
 {
 	struct evbmips_intrhand *ih;
 	uint32_t irqmask, irqstat;
Index: sys/arch/mips/ralink/ralink_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/ralink/ralink_intr.c,v
retrieving revision 1.3
diff -u -p -r1.3 ralink_intr.c
--- sys/arch/mips/ralink/ralink_intr.c	27 Sep 2011 01:02:34 -0000	1.3
+++ sys/arch/mips/ralink/ralink_intr.c	26 Aug 2016 13:45:15 -0000
@@ -291,7 +291,7 @@ ra_pic_intr(void *arg)
  * in the generic MIPS code for the timer
  */
 void
-evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending, uint32_t status)
 {
 	while (ipending != 0) {
 		const u_int bitno = 31 - __builtin_clz(ipending);
Index: sys/arch/mips/rmi/rmixl_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/rmi/rmixl_intr.c,v
retrieving revision 1.11
diff -u -p -r1.11 rmixl_intr.c
--- sys/arch/mips/rmi/rmixl_intr.c	1 Aug 2016 18:09:50 -0000	1.11
+++ sys/arch/mips/rmi/rmixl_intr.c	26 Aug 2016 13:45:16 -0000
@@ -865,7 +865,7 @@ rmixl_intr_disestablish(void *cookie)
 }
 
 void
-evbmips_iointr(int ipl, vaddr_t pc, uint32_t pending)
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t pending, uint32_t status)
 {
 	struct rmixl_cpu_softc *sc = (void *)curcpu()->ci_softc;
 
Index: sys/dev/pci/voyager/pwmclock.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/voyager/pwmclock.c,v
retrieving revision 1.10
diff -u -p -r1.10 pwmclock.c
--- sys/dev/pci/voyager/pwmclock.c	14 May 2013 09:19:36 -0000	1.10
+++ sys/dev/pci/voyager/pwmclock.c	26 Aug 2016 13:45:19 -0000
@@ -77,7 +77,6 @@ static u_int get_pwmclock_timecount(stru
 
 struct pwmclock_softc *pwmclock;
 extern void (*initclocks_ptr)(void);
-extern struct clockframe cf;
 
 /* 0, 1/4, 3/8, 1/2, 5/8, 3/4, 7/8, 1 */
 static int scale_m[] = {1, 1, 3, 1, 5, 3, 7, 1};
@@ -137,7 +136,8 @@ pwmclock_attach(device_t parent, device_
 
 	aprint_normal("\n");
 
-	voyager_establish_intr(parent, 22, pwmclock_intr, sc);
+	/* NULL here gets us the clockframe */
+	voyager_establish_intr(parent, 22, pwmclock_intr, NULL);
 	reg = voyager_set_pwm(100, 100); /* 100Hz, 10% duty cycle */
 	reg |= SM502_PWM_ENABLE | SM502_PWM_ENABLE_INTR |
 	       SM502_PWM_INTR_PENDING;
@@ -273,7 +273,8 @@ pwmclock_set_speed(struct pwmclock_softc
 int
 pwmclock_intr(void *cookie)
 {
-	struct pwmclock_softc *sc = cookie;
+	struct clockframe *cf = cookie;
+	struct pwmclock_softc *sc = pwmclock;
 	uint32_t reg, now, diff;
 
 	/* is it us? */
@@ -307,7 +308,7 @@ pwmclock_intr(void *cookie)
 		sc->sc_step = sc->sc_step_wanted;
 	}
 		 
-	hardclock(&cf);
+	hardclock(cf);
 
 	return 1;
 }