Index: sys/arch/aarch64/include/armreg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/aarch64/include/armreg.h,v
retrieving revision 1.16
diff -u -p -r1.16 armreg.h
--- sys/arch/aarch64/include/armreg.h	9 Aug 2018 10:27:17 -0000	1.16
+++ sys/arch/aarch64/include/armreg.h	12 Aug 2018 16:58:05 -0000
@@ -1026,6 +1025,19 @@ AARCH64REG_READ_INLINE2(icc_iar1_el1, s3
 #define	icc_iar1_read		reg_icc_iar1_el1_read
 #define	icc_eoi1r_write		reg_icc_eoir1_el1_write
 
+#if defined(_KERNEL)
+
+/*
+ * CPU REGISTER ACCESS
+ */
+static __inline register_t
+cpu_mpidr_aff_read(void)
+{
+
+	return reg_mpidr_el1_read() &
+	    (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0);
+}
+
 /*
  * GENERIC TIMER REGISTER ACCESS
  */
@@ -1119,5 +1130,6 @@ gtmr_cntv_cval_read(void)
 
 	return reg_cntv_cval_el0_read();
 }
+#endif /* _KERNEL */
 
 #endif /* _AARCH64_ARMREG_H_ */
Index: sys/arch/arm/cortex/gicv3.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/cortex/gicv3.c,v
retrieving revision 1.2
diff -u -p -r1.2 gicv3.c
--- sys/arch/arm/cortex/gicv3.c	11 Aug 2018 00:32:17 -0000	1.2
+++ sys/arch/arm/cortex/gicv3.c	12 Aug 2018 16:58:09 -0000
@@ -295,19 +295,12 @@ gicv3_cpu_identity(void)
 {
 	u_int aff3, aff2, aff1, aff0;
 
-#ifdef __aarch64__
-	const register_t mpidr = reg_mpidr_el1_read();
+	const register_t mpidr = cpu_mpidr_aff_read();
+
 	aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0);
 	aff1 = __SHIFTOUT(mpidr, MPIDR_AFF1);
 	aff2 = __SHIFTOUT(mpidr, MPIDR_AFF2);
 	aff3 = __SHIFTOUT(mpidr, MPIDR_AFF3);
-#else
-	const register_t mpidr = armreg_mpidr_read();
-	aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0);
-	aff1 = __SHIFTOUT(mpidr, MPIDR_AFF1);
-	aff2 = __SHIFTOUT(mpidr, MPIDR_AFF2);
-	aff3 = 0;
-#endif
 
 	return __SHIFTIN(aff0, GICR_TYPER_Affinity_Value_Aff0) |
 	       __SHIFTIN(aff1, GICR_TYPER_Affinity_Value_Aff1) |
Index: sys/arch/arm/fdt/psci_fdt.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/fdt/psci_fdt.c,v
retrieving revision 1.11
diff -u -p -r1.11 psci_fdt.c
--- sys/arch/arm/fdt/psci_fdt.c	10 Aug 2018 22:34:36 -0000	1.11
+++ sys/arch/arm/fdt/psci_fdt.c	12 Aug 2018 16:58:09 -0000
@@ -154,14 +154,6 @@ psci_fdt_preinit(void)
 }
 
 #ifdef MULTIPROCESSOR
-static bus_addr_t psci_fdt_read_mpidr_aff(void)
-{
-#ifdef __aarch64__
-	return reg_mpidr_el1_read() & (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0);
-#else
-	return armreg_mpidr_read() & (MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0);
-#endif
-}
 
 static register_t
 psci_fdt_mpstart_pa(void)
@@ -181,7 +173,7 @@ psci_fdt_bootstrap(void)
 {
 #ifdef MULTIPROCESSOR
 	extern void cortex_mpstart(void);
-	bus_addr_t mpidr, bp_mpidr;
+	uint64_t mpidr, bp_mpidr;
 	int child;
 
 	const int cpus = OF_finddevice("/cpus");
@@ -201,7 +193,7 @@ psci_fdt_bootstrap(void)
 		return;
 
 	/* MPIDR affinity levels of boot processor. */
-	bp_mpidr = psci_fdt_read_mpidr_aff();
+	bp_mpidr = cpu_mpidr_aff_read();
 
 	/* Boot APs */
 	uint32_t started = 0;
Index: sys/arch/arm/include/armreg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/include/armreg.h,v
retrieving revision 1.122
diff -u -p -r1.122 armreg.h
--- sys/arch/arm/include/armreg.h	15 Jul 2018 23:46:57 -0000	1.122
+++ sys/arch/arm/include/armreg.h	12 Aug 2018 16:58:09 -0000
@@ -908,6 +908,15 @@ ARMREG_WRITE_INLINE(tlbdataop, "p15,3,%0
 ARMREG_READ_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */
 ARMREG_WRITE_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */
 
+#if defined(_KERNEL)
+
+static inline uint64_t
+cpu_mpidr_aff_read(void)
+{
+
+	return armreg_mpidr_read() & (MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0);
+}
+
 /*
  * GENERIC TIMER register access
  */
@@ -1002,7 +1011,8 @@ gtmr_cntv_cval_read(void)
 	return armreg_cntv_cval_read();
 }
 
-#endif /* !__ASSEMBLER__ */
+#endif /* _KERNEL */
+#endif /* !__ASSEMBLER && !_RUMPKERNEL */
 
 #elif defined(__aarch64__)