Index: sys/arch/mips/mips/mipsX_subr.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mipsX_subr.S,v
retrieving revision 1.76
diff -u -p -r1.76 mipsX_subr.S
--- sys/arch/mips/mips/mipsX_subr.S	30 Jul 2016 07:10:42 -0000	1.76
+++ sys/arch/mips/mips/mipsX_subr.S	5 Aug 2016 09:53:08 -0000
@@ -2710,8 +2736,9 @@ END(MIPSX(lwp_trampoline))
  * USPACE is already in another place of TLB before that, and make
  * sure TBIS(it) in the case.
  */
+
 LEAF_NOPROFILE(MIPSX(cpu_switch_resume))
-#if !defined(ENABLE_MIPS_16KB_PAGE) && !defined(ENABLE_MIPS_8KB_PAGE)
+#if 1 || (USPACE > PAGE_SIZE)
 	INT_L	a1, L_MD_UPTE_0(a0)		# a1 = upte[0]
 #if (PGSHIFT & 1)
 	INT_ADD a2, a1, MIPS3_PG_NEXT		# a2 = upper half
Index: sys/arch/mips/mips/vm_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/vm_machdep.c,v
retrieving revision 1.150
diff -u -p -r1.150 vm_machdep.c
--- sys/arch/mips/mips/vm_machdep.c	31 Jul 2016 15:33:42 -0000	1.150
+++ sys/arch/mips/mips/vm_machdep.c	5 Aug 2016 09:53:08 -0000
@@ -115,9 +115,11 @@ cpu_lwp_fork(struct lwp *l1, struct lwp 
 		tf->tf_regs[_R_SP] = (intptr_t)stack + stacksize;
 
 	l2->l_md.md_utf = tf;
-#if (USPACE > PAGE_SIZE)
-	if (!pmap_md_direct_mapped_vaddr_p(ua2)) {
-		__CTASSERT((PGSHIFT & 1) || UPAGES % 2 == 0);
+	if (pmap_md_direct_mapped_vaddr_p(ua2)) {
+		for (u_int i = 0; i < UPAGES; i++) {
+			l2->l_md.md_upte[i] = 0;
+		}
+	} else {
 		pt_entry_t * const pte = pmap_pte_lookup(pmap_kernel(), ua2);
 		const uint32_t x = MIPS_HAS_R4K_MMU
 		    ? (MIPS3_PG_RO | MIPS3_PG_WIRED)
@@ -128,7 +130,7 @@ cpu_lwp_fork(struct lwp *l1, struct lwp 
 			l2->l_md.md_upte[i] = pte[i] & ~x;
 		}
 	}
-#endif
+
 	/*
 	 * Rig kernel stack so that it would start out in lwp_trampoline()
 	 * and call child_return() with l as an argument.  This causes the