Index: sys/arch/arm/arm/cpufunc_asm_armv7.S
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm/cpufunc_asm_armv7.S,v
retrieving revision 1.26
diff -u -p -r1.26 cpufunc_asm_armv7.S
--- sys/arch/arm/arm/cpufunc_asm_armv7.S	9 Jun 2015 08:08:14 -0000	1.26
+++ sys/arch/arm/arm/cpufunc_asm_armv7.S	27 Jul 2017 18:27:31 -0000
@@ -179,21 +179,6 @@ ENTRY_NP(armv7_icache_sync_range)
 	bx	lr
 END(armv7_icache_sync_range)
 
-/* LINTSTUB: void armv7_icache_sync_all(void); */
-ENTRY_NP(armv7_icache_sync_all)
-	/*
-	 * We assume that the code here can never be out of sync with the
-	 * dcache, so that we can safely flush the Icache and fall through
-	 * into the Dcache cleaning code.
-	 */
-	stmdb	sp!, {r0, lr}
-	bl	_C_LABEL(armv7_idcache_wbinv_all) @clean the D cache
-	ldmia	sp!, {r0, lr}
-	dsb				@ data synchronization barrier
-	isb
-	bx	lr
-END(armv7_icache_sync_all)
-
 ENTRY(armv7_dcache_wb_range)
 	mov	ip, #0
 	mcr	p15, 2, ip, c0, c0, 0	@ set cache level to L1
@@ -212,6 +197,7 @@ ENTRY(armv7_dcache_wb_range)
 	subs	r1, r1, r2
 	bhi	1b
 	dsb				@ data synchronization barrier
+	isb				@ hmm
 	bx	lr
 END(armv7_dcache_wb_range)
 
@@ -234,6 +220,7 @@ ENTRY(armv7_dcache_wbinv_range)
 	subs	r1, r1, r2
 	bhi	1b
 	dsb				@ data synchronization barrier
+	isb				@ hmm
 	bx	lr
 END(armv7_dcache_wbinv_range)
 
@@ -256,6 +243,7 @@ ENTRY(armv7_dcache_inv_range)
 	bhi	1b
 
 	dsb				@ data synchronization barrier
+	isb				@ hmm
 	bx	lr
 END(armv7_dcache_inv_range)
 
@@ -274,8 +262,9 @@ ENTRY(armv7_idcache_wbinv_range)
 	bic	r0, r0, ip		@ clear offset from start.
 	dsb
 1:
-	mcr	p15, 0, r0, c7, c5, 1	@ invalidate the I-Cache line
 	mcr	p15, 0, r0, c7, c14, 1 	@ wb and inv the D-Cache line
+	dsb
+	mcr	p15, 0, r0, c7, c5, 1	@ invalidate the I-Cache line
 	add	r0, r0, r2
 	subs	r1, r1, r2
 	bhi	1b
@@ -285,16 +274,20 @@ ENTRY(armv7_idcache_wbinv_range)
 	bx	lr
 END(armv7_idcache_wbinv_range)
 
-/* * LINTSTUB: void armv7_idcache_wbinv_all(void); */
+STRONG_ALIAS(armv7_icache_sync_all, armv7_idcache_wbinv_all)
+/* LINTSTUB: void armv7_idcache_wbinv_all(void); */
 ENTRY_NP(armv7_idcache_wbinv_all)
-	/*
-	 * We assume that the code here can never be out of sync with the
-	 * dcache, so that we can safely flush the Icache and fall through
-	 * into the Dcache purging code.
-	 */
-	dmb
+	stmdb	sp!, {r0, lr}
+	bl	_C_LABEL(armv7_dcache_wbinv_all)
+#ifdef MULTIPROCESSOR
+	mcr	p15, 0, r0, c7, c1, 0
+#else
 	mcr	p15, 0, r0, c7, c5, 0
-	b	_C_LABEL(armv7_dcache_wbinv_all)
+#endif
+	dsb
+	isb
+	ldmia	sp!, {r0, lr}
+	bx	lr
 END(armv7_idcache_wbinv_all)
 
 /*