? sys/arch/arm/arm32/pmap.c.annotated
? sys/arch/arm/arm32/pmap_machdep.c
Index: sys/arch/arm/arm32/arm32_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm32/arm32_machdep.c,v
retrieving revision 1.112
diff -u -p -r1.112 arm32_machdep.c
--- sys/arch/arm/arm32/arm32_machdep.c	16 Jul 2016 01:49:42 -0000	1.112
+++ sys/arch/arm/arm32/arm32_machdep.c	17 Jul 2016 06:03:40 -0000
@@ -750,6 +750,8 @@ mm_md_direct_mapped_phys(paddr_t pa, vad
 bool
 mm_md_page_color(paddr_t pa, int *colorp)
 {
+#ifdef __HAVE_MM_MD_CACHE_ALIASING
+#endif
 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0
 	*colorp = atop(pa & arm_cache_prefer_mask);
 
Index: sys/arch/arm/arm32/pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm32/pmap.c,v
retrieving revision 1.335
diff -u -p -r1.335 pmap.c
--- sys/arch/arm/arm32/pmap.c	14 Jul 2016 15:51:41 -0000	1.335
+++ sys/arch/arm/arm32/pmap.c	17 Jul 2016 06:03:44 -0000
@@ -822,6 +822,7 @@ static inline void
 pmap_tlb_flushID(pmap_t pm)
 {
 #ifdef ARM_MMU_EXTENDED
+	/* XXXNH */
 	pmap_tlb_asid_release_all(pm);
 #else
 	if (pm->pm_cstate.cs_tlb_id) {
@@ -5034,13 +5035,21 @@ pmap_update(pmap_t pm)
 				    cpu_index(ci));
 			}
 		}
+
 		KASSERT(kcpuset_iszero(pm->pm_onproc));
-#endif
+		/* Assume one TLB for now */
+		CTASSERT(PMAP_TLB_MAX == 1);
 		struct pmap_asid_info * const pai =
 		    PMAP_PAI(pm, cpu_tlb_info(ci));
 
 		tlb_invalidate_asids(pai->pai_asid, pai->pai_asid);
 
+#endif
+		/*
+		 * For the UP case pmap_tlb_asid_release_all flushes
+		 * the TLB
+		 */
+		pmap_tlb_asid_release_all(pm);
 #else
 		/*
 		 * Finish up the pmap_remove_all() optimisation by flushing
@@ -5125,6 +5134,7 @@ pmap_destroy(pmap_t pm)
 		return;
 
 	if (pm->pm_remove_all) {
+		/* XXX ARM_MMU_EXTENDED */
 		pmap_tlb_flushID(pm);
 		pm->pm_remove_all = false;
 	}