Index: sys/arch/aarch64/aarch64/pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/aarch64/aarch64/pmap.c,v
retrieving revision 1.34
diff -u -p -r1.34 pmap.c
--- sys/arch/aarch64/aarch64/pmap.c	21 Dec 2018 08:01:01 -0000	1.34
+++ sys/arch/aarch64/aarch64/pmap.c	2 Feb 2019 11:43:48 -0000
@@ -1295,9 +1295,7 @@ _pmap_enter(struct pmap *pm, vaddr_t va,
 	struct pv_entry *spv, *opv = NULL;
 	pd_entry_t pde;
 	pt_entry_t attr, pte, *ptep;
-#ifdef UVMHIST
 	pt_entry_t opte;
-#endif
 	pd_entry_t *l0, *l1, *l2, *l3;
 	paddr_t pdppa;
 	uint32_t mdattr;
@@ -1404,9 +1402,7 @@ _pmap_enter(struct pmap *pm, vaddr_t va,
 	ptep = &l3[idx];	/* as PTE */
 
 	pte = *ptep;
-#ifdef UVMHIST
 	opte = pte;
-#endif
 	need_sync_icache = (prot & VM_PROT_EXECUTE);
 
 #ifdef KASAN
@@ -1504,23 +1500,25 @@ _pmap_enter(struct pmap *pm, vaddr_t va,
 
 	pte = pa | attr;
 
-	if (need_sync_icache) {
-		/* non-exec -> exec */
-		UVMHIST_LOG(pmaphist,
-		    "icache_sync: pm=%p, va=%016lx, pte: %016lx -> %016lx",
-		    pm, va, opte, pte);
-		if (!l3pte_writable(pte)) {
-			PTE_ICACHE_SYNC_PAGE(pte, ptep, pm, va, l3only);
-			atomic_swap_64(ptep, pte);
-			AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va ,true);
-		} else {
-			atomic_swap_64(ptep, pte);
+	if (pte != opte) {
+		atomic_swap_64(ptep, 0);
+		if (l3pte_valid(opte))	
 			AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, l3only);
-			cpu_icache_sync_range(va, PAGE_SIZE);
-		}
-	} else {
+
 		atomic_swap_64(ptep, pte);
-		AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, l3only);
+		if (need_sync_icache) {
+			/* non-exec -> exec */
+			UVMHIST_LOG(pmaphist,
+			   "icache_sync: pm=%p, va=%016lx, pte: %016lx -> %016lx",
+			   pm, va, opte, pte);
+			if (!l3pte_writable(pte)) {
+				PTE_ICACHE_SYNC_PAGE(pte, ptep, pm, va, l3only);
+				atomic_swap_64(ptep, pte);
+				AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va ,true);
+			} else {
+				cpu_icache_sync_range(va, PAGE_SIZE);
+			}
+		}
 	}
 
 	if (pte & LX_BLKPAG_OS_WIRED)