Index: sys/arch/arm/cortex/a9_mpsubr.S
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/cortex/a9_mpsubr.S,v
retrieving revision 1.35
diff -u -p -r1.35 a9_mpsubr.S
--- sys/arch/arm/cortex/a9_mpsubr.S	27 Apr 2015 07:13:44 -0000	1.35
+++ sys/arch/arm/cortex/a9_mpsubr.S	27 Apr 2015 09:34:43 -0000
@@ -180,9 +180,25 @@ arm_cpuinit:
 
 	mcr	p15, 0, r2, c1, c0, 0	// SCTLR write
 
+#if 0
+	// Sequence for SCTRL write
+	// sctrl; isb; invalidate cache; isb
+	isb
+
+	mcr     p15, 0, r1, c7, c5, 0	// invalidate I cache
+	isb
+	mcr	p15, 0, r1, c8, c7, 0	// TLBIALL (just this core)
+	mcr	p15, 0, r1, c7, c5, 6	// BPIALL (just this core)
+	isb
+#endif
 	XPUTC(#'F')
 	dsb				// Drain the write buffers.
 
+	XPUTC(#'C')
+	mov	r1, #0			// get KERNEL_PID
+	mcr	p15, 0, r1, c13, c0, 1	// CONTEXTIDR write
+	isb
+
 	XPUTC(#'G')
 	mrc	p15, 0, r1, c0, c0, 5	// MPIDR read
 	cmp	r1, #0
@@ -209,17 +225,11 @@ arm_cpuinit:
 
 	isb
 
-#if !defined(CPU_CORTEXA5)
-	XPUTC(#'I')
 	mov	r1, #0
 	mcr	p15, 0, r1, c8, c7, 0	// TLBIALL (just this core)
+	mcr	p15, 0, r1, c7, c5, 6	// BPIALL (just this core)
 	dsb
 	isb
-#endif
-
-	XPUTC(#'J')
-	mov	r1, #0			// get KERNEL_PID
-	mcr	p15, 0, r1, c13, c0, 1	// CONTEXTIDR write
 
 	// Set the Domain Access register.  Very important!
 	XPUTC(#'K')