Index: sys/arch/arm/arm/cpufunc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm/cpufunc.c,v
retrieving revision 1.182
diff -u -p -r1.182 cpufunc.c
--- sys/arch/arm/arm/cpufunc.c	13 Nov 2021 01:48:12 -0000	1.182
+++ sys/arch/arm/arm/cpufunc.c	13 Nov 2021 11:57:28 -0000
@@ -3007,7 +3005,31 @@ armv7_setup(char *args)
 		    0;
 	} else if (CPU_ID_CORTEX_A12_P(lcputype) ||
 		   CPU_ID_CORTEX_A17_P(lcputype)) {
+
 		actlr_set = CORTEXA17_ACTLR_SMP;
+		uint32_t diagset = 0;
+		uint32_t dgnctlr1 = armreg_dgnctlr1_read();
+		uint16_t varrev =
+		   __SHIFTIN(__SHIFTOUT(lcputype, CPU_ID_VARIANT_MASK), __BITS(7,4)) |
+		   __SHIFTIN(__SHIFTOUT(lcputype, CPU_ID_REVISION_MASK), __BITS(3,0)) |
+		   0;
+		/* Errata 852421 exists upto r1p2 */
+		if (varrev < 0x12) {
+			diagset |= __BIT(24);
+		}
+		/* Errata 852423 exists upto r1p2*/
+		if (varrev < 0x12) {
+			diagset |= __BIT(12);
+		}
+		/* Errata 857272 */
+		diagset |= __BITS(11,10);
+
+		armreg_dgnctlr1_write(dgnctlr1 | diagset);
+
+		/* Clear out the cache */
+		cpu_idcache_wbinv_all();
+
+
 	} else if (CPU_ID_CORTEX_A53_P(lcputype)) {
 	} else if (CPU_ID_CORTEX_A57_P(lcputype)) {
 	} else if (CPU_ID_CORTEX_A72_P(lcputype)) {
Index: sys/arch/arm/include/armreg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/include/armreg.h,v
retrieving revision 1.133
diff -u -p -r1.133 armreg.h
--- sys/arch/arm/include/armreg.h	13 Nov 2021 01:48:12 -0000	1.133
+++ sys/arch/arm/include/armreg.h	13 Nov 2021 11:57:28 -0000
@@ -927,6 +927,16 @@ ARMREG_READ_INLINE(tlbdata1, "p15,3,%0,c
 ARMREG_READ_INLINE(tlbdata2, "p15,3,%0,c15,c0,2") /* TLB Data Register 2 (cortex) */
 ARMREG_WRITE_INLINE(tlbdataop, "p15,3,%0,c15,c4,2") /* TLB Data Read Operation (cortex) */
 
+ARMREG_READ_INLINE(dgnctlr0, "p15,0,%0,c15,c0,0")	/* DGNCTLR0 */
+ARMREG_WRITE_INLINE(dgnctlr0, "p15,0,%0,c15,c0,0")	/* DGNCTLR0 */
+ARMREG_READ_INLINE(dgnctlr1, "p15,0,%0,c15,c0,1")	/* DGNCTLR1 */
+ARMREG_WRITE_INLINE(dgnctlr1, "p15,0,%0,c15,c0,1")	/* DGNCTLR1 */
+ARMREG_READ_INLINE(dgnctlr2, "p15,0,%0,c15,c0,2")	/* DGNCTLR2 */
+ARMREG_WRITE_INLINE(dgnctlr2, "p15,0,%0,c15,c0,2")	/* DGNCTLR2 */
+ARMREG_READ_INLINE(dgnctlr3, "p15,0,%0,c15,c0,3")	/* DGNCTLR3 */
+ARMREG_WRITE_INLINE(dgnctlr3, "p15,0,%0,c15,c0,3")	/* DGNCTLR3 */
+
+
 ARMREG_READ_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */
 ARMREG_WRITE_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */