Index: arch/arm/arm/cpufunc_asm_armv7.S
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm/cpufunc_asm_armv7.S,v
retrieving revision 1.24
diff -u -p -r1.24 cpufunc_asm_armv7.S
--- arch/arm/arm/cpufunc_asm_armv7.S	30 May 2015 21:25:22 -0000	1.24
+++ arch/arm/arm/cpufunc_asm_armv7.S	2 Jun 2015 13:41:13 -0000
@@ -94,6 +94,13 @@ ENTRY(armv7_tlb_flushID_SE)
 #endif
 #endif /* !MULTIPROCESSOR */
 	dsb				@ data synchronization barrier
+
+
+	mov	r0, #0
+	// A15 Errata 798181
+	mcr	p15, 0, r0, c8, c3, 1
+	dsb
+
 	isb
 	bx	lr
 END(armv7_tlb_flushID_SE)
@@ -102,6 +109,11 @@ ENTRY(armv7_tlb_flushD)
 	mov	r0, #0
 	mcr	p15, 0, r0, c8, c6, 0	@ flush entire D tlb
 	dsb				@ data synchronization barrier
+
+	// A15 Errata 798181
+	mcr	p15, 0, r0, c8, c3, 1
+	dsb
+
 	isb
 	bx      lr
 END(armv7_tlb_flushD)
@@ -118,6 +130,11 @@ ENTRY(armv7_tlb_flushID)
 	mcr	p15, 0, r0, c7, c5, 6	@ branch predictor invalidate
 #endif
 	dsb				@ data synchronization barrier
+
+	// A15 Errata 798181
+	mcr	p15, 0, r0, c8, c3, 1
+	dsb
+
 	isb
 	bx      lr
 END(armv7_tlb_flushID)
Index: arch/arm/arm32/arm32_tlb.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm32/arm32_tlb.c,v
retrieving revision 1.9
diff -u -p -r1.9 arm32_tlb.c
--- arch/arm/arm32/arm32_tlb.c	26 Mar 2015 08:45:05 -0000	1.9
+++ arch/arm/arm32/arm32_tlb.c	2 Jun 2015 13:41:13 -0000
@@ -99,6 +99,13 @@ tlb_invalidate_asids(tlb_asid_t lo, tlb_
 			armreg_tlbiasid_write(lo);
 #endif
 		}
+		arm_dsb();
+#ifdef MULTIPROCESSOR
+		/* A15 errata 798181 */
+		armreg_tlbimvais_write(0);
+		arm_dsb();
+#endif
+
 		arm_isb();
 		if (__predict_false(vivt_icache_p)) {
 #ifdef MULTIPROCESSOR
@@ -131,6 +138,11 @@ tlb_invalidate_addr(vaddr_t va, tlb_asid
 		//armreg_tlbiall_write(asid);
 	}
 	arm_dsb();
+
+	/* A15 errata 798181 */
+	armreg_tlbimvais_write(0);
+	arm_dsb();
+
 	arm_isb();
 }