From be76051742221b98e991b5985e3b8e441ebb8072 Mon Sep 17 00:00:00 2001 From: Nick Hudson Date: Thu, 11 Nov 2021 07:17:02 +0000 Subject: [PATCH 1/9] Octeon cache fixes --- sys/arch/mips/include/cache_octeon.h | 3 ++- sys/arch/mips/mips/cache.c | 25 +++++++++++++++++++++---- sys/arch/mips/mips/cache_octeon.c | 22 ++++++++++++++++------ 3 files changed, 39 insertions(+), 11 deletions(-) diff --git a/sys/arch/mips/include/cache_octeon.h b/sys/arch/mips/include/cache_octeon.h index 481a94806b88..f55815aedd37 100644 --- a/sys/arch/mips/include/cache_octeon.h +++ b/sys/arch/mips/include/cache_octeon.h @@ -24,7 +24,8 @@ * Dcache. */ #define OCTEON_I_DCACHE_WAYS 64 -#define OCTEON_I_DCACHE_SETS 2 +#define OCTEON_I_DCACHE_SETS 1 +#define OCTEON_I_PLUS_DCACHE_SETS 2 #define OCTEON_II_DCACHE_SETS 8 #define OCTEON_II_DCACHE_WAYS 32 diff --git a/sys/arch/mips/mips/cache.c b/sys/arch/mips/mips/cache.c index d9eae314d002..b1a2d609413c 100644 --- a/sys/arch/mips/mips/cache.c +++ b/sys/arch/mips/mips/cache.c @@ -1395,24 +1395,39 @@ mips_config_cache_modern(uint32_t cpu_id) case MIPS_CN38XX: case MIPS_CN31XX: case MIPS_CN30XX: + /* OCTEON */ + case MIPS_CN50XX: case MIPS_CN52XX: case MIPS_CN58XX: case MIPS_CN56XX: - /* OCTEON and OCTEON Plus */ + /* OCTEON Plus */ /* Dcache on cnMIPS core doesn't follow spec */ mci->mci_pdcache_line_size = OCTEON_CACHELINE_SIZE; mci->mci_pdcache_ways = OCTEON_I_DCACHE_WAYS; + int octeon1_sets = 0; + switch (MIPS_PRID_IMPL(cpu_id)) { + case MIPS_CN38XX: + case MIPS_CN31XX: + case MIPS_CN30XX: + octeon1_sets = OCTEON_I_DCACHE_SETS; + break; + case MIPS_CN50XX: + case MIPS_CN52XX: + case MIPS_CN58XX: + case MIPS_CN56XX: + octeon1_sets = OCTEON_I_PLUS_DCACHE_SETS; + break; + } mci->mci_pdcache_way_size = - OCTEON_I_DCACHE_SETS * OCTEON_CACHELINE_SIZE; + octeon1_sets * OCTEON_CACHELINE_SIZE; mci->mci_pdcache_write_through = true; /* Icache on cnMIPS core does follows MIPS spec */ - + KASSERT(mci->mci_picache_vivt); break; - /* XXX cnMIPS II cores not yet tested */ case MIPS_CN61XX: case MIPS_CN63XX: case MIPS_CN66XX: @@ -1430,6 +1445,7 @@ mips_config_cache_modern(uint32_t cpu_id) mci->mci_picache_ways = OCTEON_II_ICACHE_WAYS; mci->mci_picache_way_size = OCTEON_II_ICACHE_SETS * OCTEON_CACHELINE_SIZE; + KASSERT(mci->mci_picache_vivt); break; case MIPS_CN70XX: @@ -1448,6 +1464,7 @@ mips_config_cache_modern(uint32_t cpu_id) mci->mci_picache_ways = OCTEON_III_ICACHE_WAYS; mci->mci_picache_way_size = OCTEON_CACHELINE_SIZE * OCTEON_III_ICACHE_SETS; + KASSERT(mci->mci_picache_vivt); break; default: diff --git a/sys/arch/mips/mips/cache_octeon.c b/sys/arch/mips/mips/cache_octeon.c index c80b31e2efa0..4f8fbb0cae78 100644 --- a/sys/arch/mips/mips/cache_octeon.c +++ b/sys/arch/mips/mips/cache_octeon.c @@ -6,6 +6,8 @@ __KERNEL_RCSID(0, "$NetBSD: cache_octeon.c,v 1.4 2020/06/06 14:30:44 simonb Exp #include #include +#include + #include #include #include @@ -21,6 +23,7 @@ int octeon_cache_debug = 0; #define ICACHE_DEBUG_PRINTF(x) /* nothing */ #endif +void octeon_icache_sync_local(void); static inline void mips_synci(vaddr_t va) @@ -30,21 +33,29 @@ mips_synci(vaddr_t va) } void -octeon_icache_sync_all(void) +octeon_icache_sync_local(void) { - ICACHE_DEBUG_PRINTF(("%s\n", __func__)); mips_synci(MIPS_KSEG0_START); SYNC; } + +void +octeon_icache_sync_all(void) +{ + uint64_t where; + + ICACHE_DEBUG_PRINTF(("%s\n", __func__)); + where = xc_broadcast(0, (xcfunc_t)octeon_icache_sync_local, NULL, NULL); + xc_wait(where); +} void octeon_icache_sync_range(register_t va, vsize_t size) { ICACHE_DEBUG_PRINTF(("%s: va=%#"PRIxREGISTER", size=%#"PRIxVSIZE"\n", __func__, va, size)); - mips_synci(MIPS_KSEG0_START); - SYNC; + octeon_icache_sync_all(); } void @@ -53,8 +64,7 @@ octeon_icache_sync_range_index(vaddr_t va, vsize_t size) ICACHE_DEBUG_PRINTF(("%s: va=%#"PRIxVADDR", size=%#"PRIxVSIZE"\n", __func__, va, size)); - mips_synci(MIPS_KSEG0_START); - SYNC; + octeon_icache_sync_all(); } void -- 2.25.1