Index: sys/arch/arm/arm32/bus_dma.c
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/arm32/bus_dma.c,v
retrieving revision 1.113
diff -p -u -r1.113 bus_dma.c
--- sys/arch/arm/arm32/bus_dma.c	14 Sep 2018 10:13:02 -0000	1.113
+++ sys/arch/arm/arm32/bus_dma.c	7 Jan 2019 08:53:32 -0000
@@ -1421,26 +1421,42 @@ _bus_dmamem_map(bus_dma_tag_t t, bus_dma
 		for (pa = segs[curseg].ds_addr;
 		    pa < (segs[curseg].ds_addr + segs[curseg].ds_len);
 		    pa += PAGE_SIZE, va += PAGE_SIZE, size -= PAGE_SIZE) {
-			bool uncached = (flags & BUS_DMA_COHERENT);
+			int pmap_flags = 0;
+
 #ifdef DEBUG_DMA
 			printf("wiring p%lx to v%lx", pa, va);
 #endif	/* DEBUG_DMA */
+
 			if (size == 0)
 				panic("_bus_dmamem_map: size botch");
 
-			const struct arm32_dma_range * const dr =
-			    _bus_dma_paddr_inrange(t->_ranges, t->_nranges, pa);
+#ifdef ARMV6_CACHED_DMA_MEMORY
 			/*
-			 * If this dma region is coherent then there is
-			 * no need for an uncached mapping.
+			 * Force cached mapping for ARMv6+, which allows us
+			 * unaligned access to DMA buffer.
 			 */
-			if (dr != NULL
-			    && (dr->dr_flags & _BUS_DMAMAP_COHERENT)) {
-				uncached = false;
+			if (!CPU_IS_ARMV6_P() && !CPU_IS_ARMV7_P())
+#endif
+			{
+				bool uncached = (flags & BUS_DMA_COHERENT);
+
+				const struct arm32_dma_range * const dr =
+				    _bus_dma_paddr_inrange(t->_ranges,
+					t->_nranges, pa);
+				/*
+				 * If this DMA region is coherent then there is
+				 * no need for an uncached mapping.
+				 */
+				if (dr != NULL
+				    && (dr->dr_flags & _BUS_DMAMAP_COHERENT))
+					uncached = false;
+
+				if (uncached)
+					pmap_flags = PMAP_NOCACHE;
 			}
 
 			pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE,
-			    PMAP_WIRED | (uncached ? PMAP_NOCACHE : 0));
+			    PMAP_WIRED | pmap_flags);
 		}
 	}
 	pmap_update(pmap_kernel());
Index: sys/arch/arm/conf/Makefile.arm
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/conf/Makefile.arm,v
retrieving revision 1.49
diff -p -u -r1.49 Makefile.arm
--- sys/arch/arm/conf/Makefile.arm	22 Sep 2018 12:24:01 -0000	1.49
+++ sys/arch/arm/conf/Makefile.arm	7 Jan 2019 09:03:58 -0000
@@ -53,6 +53,17 @@ CPPFLAGS.cpufunc_asm_armv6.S+=	-mcpu=arm
 CPPFLAGS.cpufunc_asm_arm11.S+=	-mcpu=arm1136j-s
 CPPFLAGS.cpufunc_asm_xscale.S+=	-mcpu=xscale
 
+.if !empty(MACHINE_ARCH:Mearmv6*) || !empty(MACHINE_ARCH:Mearmv7*)
+. if ARMV6_CACHED_DMA_MEMORY
+# Use cached memory for DMA on ARMv6+, which allows us unaligned
+# access to DMA buffer.
+CPPFLAGS+=	-DARMV6_CACHED_DMA_MEMORY
+. else
+# Otherwise, we need strictly-aligned access to DMA buffer.
+CFLAGS+=	-mno-unaligned-access
+. endif
+.endif
+
 ##
 ## (3) libkern and compat
 ##
Index: sys/arch/arm/conf/std.arm
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/conf/std.arm,v
retrieving revision 1.5
diff -p -u -r1.5 std.arm
--- sys/arch/arm/conf/std.arm	18 Dec 2017 15:53:38 -0000	1.5
+++ sys/arch/arm/conf/std.arm	7 Jan 2019 09:57:12 -0000
@@ -3,3 +3,8 @@
 # standard NetBSD/arm options
 
 options		CPU_IN_CKSUM
+
+# Use cached memory for bus_dma(9) on ARMv6+, which allows us unaligned
+# access to DMA buffer.
+# XXX This breaks drivers that do not invalidate cache appropriately.
+#makeoptions	ARMV6_CACHED_DMA_MEMORY=1