Index: arch/amd64/include/proc.h =================================================================== RCS file: /cvsroot/src/sys/arch/amd64/include/proc.h,v retrieving revision 1.19 diff -u -r1.19 proc.h --- arch/amd64/include/proc.h 20 Feb 2014 18:19:10 -0000 1.19 +++ arch/amd64/include/proc.h 9 Dec 2016 22:39:19 -0000 @@ -38,6 +38,7 @@ #include #include +#include /* * Machine-dependent part of the lwp structure for amd64. @@ -60,10 +61,12 @@ int md_flags; /* Syscall handling function */ void (*md_syscall)(struct trapframe *); + struct x86_hw_watchpoint md_watchpoint[X86_HW_WATCHPOINTS]; }; /* md_flags */ -#define MDP_USEDMTRR 0x0008 /* has set volatile MTRRs */ +#define MDP_USEDMTRR 0x0008 /* has set volatile MTRRs */ +#define MDP_HWWATCHPOINTS 0x0010 /* has hardware watchpoints */ #else /* __x86_64__ */ Index: arch/amd64/include/ptrace.h =================================================================== RCS file: /cvsroot/src/sys/arch/amd64/include/ptrace.h,v retrieving revision 1.7 diff -u -r1.7 ptrace.h --- arch/amd64/include/ptrace.h 19 Oct 2016 09:44:00 -0000 1.7 +++ arch/amd64/include/ptrace.h 9 Dec 2016 22:39:19 -0000 @@ -36,18 +36,24 @@ /* * i386-dependent ptrace definitions */ -#define PT_STEP (PT_FIRSTMACH + 0) -#define PT_GETREGS (PT_FIRSTMACH + 1) -#define PT_SETREGS (PT_FIRSTMACH + 2) -#define PT_GETFPREGS (PT_FIRSTMACH + 3) -#define PT_SETFPREGS (PT_FIRSTMACH + 4) +#define PT_STEP (PT_FIRSTMACH + 0) +#define PT_GETREGS (PT_FIRSTMACH + 1) +#define PT_SETREGS (PT_FIRSTMACH + 2) +#define PT_GETFPREGS (PT_FIRSTMACH + 3) +#define PT_SETFPREGS (PT_FIRSTMACH + 4) +#define PT_GETWATCHPOINT (PT_FIRSTMACH + 5) +#define PT_SETWATCHPOINT (PT_FIRSTMACH + 6) +#define PT_NUMWATCHPOINTS (PT_FIRSTMACH + 7) #define PT_MACHDEP_STRINGS \ "PT_STEP", \ "PT_GETREGS", \ "PT_SETREGS", \ "PT_GETFPREGS", \ - "PT_SETFPREGS", + "PT_SETFPREGS", \ + "PT_GETWATCHPOINT", \ + "PT_SETWATCHPOINT", \ + "PT_NUMWATCHPOINTS" #include #define PTRACE_REG_PC(r) (r)->regs[_REG_RIP] @@ -59,6 +65,31 @@ #define PTRACE_BREAKPOINT_SIZE 1 #define PTRACE_BREAKPOINT_ADJ 1 +/* + * This MD structure translates into and from x86_hw_watchpoint + * + * pw_lwpid - 0 matches all LWPs within a process + * pw_address - 0 means disabled hardware watchpoint + * + * conditions: + * 0b00 - execution + * 0b01 - data write + * 0b10 - io read/write (not implemented) + * 0b11 - data read/write + * + * length: + * 0b00 - 1 byte + * 0b01 - 2 bytes + * 0b10 - undefined + * 0b11 - 4 bytes + */ +typedef struct ptrace_watchpoint { + lwpid_t pw_lwpid; + void *pw_address; + int pw_condition; + int pw_length; +} ptrace_watchpoint_t; + #ifdef _KERNEL_OPT #include "opt_compat_netbsd32.h" Index: arch/amd64/include/userret.h =================================================================== RCS file: /cvsroot/src/sys/arch/amd64/include/userret.h,v retrieving revision 1.9 diff -u -r1.9 userret.h --- arch/amd64/include/userret.h 28 Apr 2008 20:23:12 -0000 1.9 +++ arch/amd64/include/userret.h 9 Dec 2016 22:39:19 -0000 @@ -67,6 +67,7 @@ */ #include +#include static __inline void userret(struct lwp *); @@ -77,7 +78,26 @@ static __inline void userret(struct lwp *l) { + struct proc *p; + size_t i; /* Invoke MI userret code */ mi_userret(l); + + p = l->l_proc; + + mutex_enter(p->p_lock); + if (p->p_md.md_flags & MDP_HWWATCHPOINTS) { + for (i = 0; i < X86_HW_WATCHPOINTS; i++) { + if (p->p_md.md_watchpoint[i].address != 0 && + (p->p_md.md_watchpoint[i].lwpid == 0 || + p->p_md.md_watchpoint[i].lwpid == l_lid)) { + set_x86_hw_watchpoint(i, + p->p_md.md_watchpoint[i].address, + p->p_md.md_watchpoint[i].condition, + p->p_md.md_watchpoint[i].length); + } + } + } + mutex_exit(p->p_lock); } Index: arch/x86/include/Makefile =================================================================== RCS file: /cvsroot/src/sys/arch/x86/include/Makefile,v retrieving revision 1.20 diff -u -r1.20 Makefile --- arch/x86/include/Makefile 27 Feb 2016 00:09:45 -0000 1.20 +++ arch/x86/include/Makefile 9 Dec 2016 22:39:27 -0000 @@ -11,6 +11,7 @@ cpu_ucode.h \ cputypes.h \ cpuvar.h \ + dbregs.h \ float.h \ fpu.h \ ieee.h ieeefp.h \ Index: arch/x86/include/dbregs.h =================================================================== RCS file: /cvsroot/src/sys/arch/x86/include/dbregs.h,v retrieving revision 1.1 diff -u -r1.1 dbregs.h --- arch/x86/include/dbregs.h 27 Nov 2016 14:49:21 -0000 1.1 +++ arch/x86/include/dbregs.h 9 Dec 2016 22:39:27 -0000 @@ -32,14 +32,77 @@ #ifdef _KERNEL -struct lwp; -struct dbreg; +#include -void reset_dbregs(void); +#define X86_HW_WATCHPOINTS 4 -int process_write_dbregs(struct lwp *lwp, const struct dbreg *regs); -int process_read_dbregs(struct lwp *lwp, struct dbreg *regs); +/* + * lwpid - 0 means all LWPs in a process + * address - 0 means that watchpoint is disabled + */ +struct x86_hw_watchpoint { + lwpid_t lwpid; + vaddr_t address; + enum x86_hw_watchpoint_condition condition; + enum x86_hw_watchpoint_length length; +}; + +#define X86_HW_WATCHPOINT_LOCAL_DR0_BREAKPOINT _BIT(0) +#define X86_HW_WATCHPOINT_GLOBAL_DR0_BREAKPOINT _BIT(1) +#define X86_HW_WATCHPOINT_LOCAL_DR1_BREAKPOINT _BIT(2) +#define X86_HW_WATCHPOINT_GLOBAL_DR1_BREAKPOINT _BIT(3) +#define X86_HW_WATCHPOINT_LOCAL_DR2_BREAKPOINT _BIT(4) +#define X86_HW_WATCHPOINT_GLOBAL_DR2_BREAKPOINT _BIT(5) +#define X86_HW_WATCHPOINT_LOCAL_DR3_BREAKPOINT _BIT(6) /* old */ +#define X86_HW_WATCHPOINT_GLOBAL_DR3_BREAKPOINT _BIT(7) +#define X86_HW_WATCHPOINT_LOCAL_EXACT_BREAKPOINT _BIT(8) +#define X86_HW_WATCHPOINT_GLOBAL_EXACT_BREAKPOINT _BIT(9) +/* undefined _BIT(10) */ +#define X86_HW_WATCHPOINT_RESTRICTED_TRANSACTIONAL_MEMORY _BIT(11) +/* undefined _BIT(12) */ +#define X86_HW_WATCHPOINT_GENERAL_DETECT_ENABLE _BIT(13) +/* undefined _BITS(14,15) */ + +#define X86_HW_WATCHPOINT_DR0_CONDITION_MASK _BITS(16, 17) +#define X86_HW_WATCHPOINT_DR0_LENGTH_MASK _BITS(18, 19) +#define X86_HW_WATCHPOINT_DR1_CONDITION_MASK _BITS(20, 21) +#define X86_HW_WATCHPOINT_DR1_LENGTH_MASK _BITS(22, 23) +#define X86_HW_WATCHPOINT_DR2_CONDITION_MASK _BITS(24, 25) +#define X86_HW_WATCHPOINT_DR2_LENGTH_MASK _BITS(26, 27) +#define X86_HW_WATCHPOINT_DR3_CONDITION_MASK _BITS(28, 29) +#define X86_HW_WATCHPOINT_DR3_LENGTH_MASK _BITS(30, 31) + +/* + * X86_HW_WATCHPOINT_CONDITION_IO_READWRITE is unused + * it requires DE (debug extension) flag in control register CR4 set + * not all CPUs support it + */ +enum x86_hw_watchpoint_condition { + X86_HW_WATCHPOINT_CONDITION_EXECUTION = 0x0, + X86_HW_WATCHPOINT_CONDITION_DATA_WRITE = 0x1, + X86_HW_WATCHPOINT_CONDITION_IO_READWRITE = 0x2, + X86_HW_WATCHPOINT_CONDITION_DATA_READWRITE = 0x3 +}; + +enum x86_hw_watchpoint_length { + X86_HW_WATCHPOINT_LENGTH_BYTE = 0x0, + X86_HW_WATCHPOINT_LENGTH_TWOBYTES = 0x1, + /* 0x2 undefined */ + X86_HW_WATCHPOINT_LENGTH_FOURBYTES = 0x3 +}; + +/* + * Set CPU Debug Registers - to be used before entering user-land context + */ +void set_x86_hw_watchpoint(size_t idx, vaddr_t address, + enum x86_hw_watchpoint_condition condition, + enum x86_hw_watchpoint_length length); + +/* + * Reset CPU Debug Registers - to be used after entering kernel context + */ +void clear_x86_hw_watchpoints(void); #endif -#endif /* _X86_FPU_H_ */ +#endif /* _X86_DBREGS_H_ */ Index: arch/x86/x86/dbregs.c =================================================================== RCS file: arch/x86/x86/dbregs.c diff -N arch/x86/x86/dbregs.c --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ arch/x86/x86/dbregs.c 9 Dec 2016 22:39:27 -0000 @@ -0,0 +1,100 @@ +/* $NetBSD: dbregs.h,v 1.1 2016/11/27 14:49:21 kamil Exp $ */ + +/*- + * Copyright (c) 2016 The NetBSD Foundation, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include + +void +set_x86_watchpoint(size_t idx, vaddr_t address, + enum x86_hw_watchpoint_condition condition, + enum x86_hw_watchpoint_length length) +{ + register_t dr; + + /* Read the original DR7 value in order to save existing watchpoints */ + dr = rdr7(); + + switch (idx) { + case 0: + ldr0(address); + dr |= X86_HW_WATCHPOINT_GLOBAL_DR0_BREAKPOINT; + dr |= __SHIFTIN(condition, + X86_HW_WATCHPOINT_DR0_CONDITION_MASK); + dr |= __SHIFTIN(length, + X86_HW_WATCHPOINT_DR0_LENGTH_MASK); + break; + case 1: + ldr1(address); + dr |= X86_HW_WATCHPOINT_GLOBAL_DR1_BREAKPOINT; + dr |= __SHIFTIN(condition, + X86_HW_WATCHPOINT_DR1_CONDITION_MASK); + dr |= __SHIFTIN(length, + X86_HW_WATCHPOINT_DR1_LENGTH_MASK); + break; + case 2: + ldr2(address); + dr |= X86_HW_WATCHPOINT_GLOBAL_DR2_BREAKPOINT; + dr |= __SHIFTIN(condition, + X86_HW_WATCHPOINT_DR2_CONDITION_MASK); + dr |= __SHIFTIN(length, + X86_HW_WATCHPOINT_DR2_LENGTH_MASK); + break; + case 3: + ldr3(address); + dr |= X86_HW_WATCHPOINT_GLOBAL_DR3_BREAKPOINT; + dr |= __SHIFTIN(condition, + X86_HW_WATCHPOINT_DR3_CONDITION_MASK); + dr |= __SHIFTIN(length, + X86_HW_WATCHPOINT_DR3_LENGTH_MASK); + break; + } + + ldr7(dr); +} + +void +clear_x86_hw_watchpoints(void) +{ + + /* + * It's sufficient to just disable Debug Control Register bits to + * deactivate hardware watchpoints + */ + ldr7(0); + /* + * However at some point we need to clear also other Debug Registers + * do it now + */ + ldr0(0); + ldr1(0); + ldr2(0); + ldr3(0); + ldr6(0); +}